The Marion system for retargetable instruction scheduling

Marion is a retargetable code generator system designed specifically for RISCS. Each code generator is built from a machine description that includes code selection and code scheduling information in a concise and readable format. The description language is designed to be easy to use, yet rich enough to support a broad range of RISCS. We have used Marion to produce code generators containing good instruction schedulers for the Motorola 88000, the MIPS R2000 and the Intel i860. Given this enabling technology, we have experimented with alternative architectures and different strategies for instruction scheduling and register allocation. This paper describes the Marion system and machine description language, with particular emphasis on instruction scheduling,

[1]  David Gordon Bradlee,et al.  Retargetable instruction scheduling for pipelined processors , 1991 .

[2]  P ? ? ? ? ? ? ? % ? ? ? ? , 1991 .

[3]  Susan J. Eggers,et al.  The effect on RISC performance of register set size and structure versus code generation strategy , 1991, ISCA '91.

[4]  G. G. Stokes "J." , 1890, The New Yale Book of Quotations.

[5]  Philippe Aigrain,et al.  Experience with a Graham-Glanville style code generator , 1984, SIGPLAN '84.

[6]  J. F. Thorlin Code generation for PIE (Parallel Instruction Execution) computers , 1967, AFIPS '67 (Spring).

[7]  Alexandru Nicolau,et al.  Parallel processing: a smart compiler and a dumb machine , 1984, SIGPLAN '84.

[8]  Christopher W. Fraser,et al.  A code generation interface for ANSI C , 1991, Softw. Pract. Exp..

[9]  Wen-mei W. Hwu,et al.  Exploiting parallel microprocessor microarchitectures with a compiler code generator , 1988, ISCA '88.

[10]  John L. Hennessy,et al.  Register allocation by priority-based coloring , 1984, SIGPLAN '84.

[11]  Roy F. Touzeau A Fortran compiler for the FPS-164 scientific computer , 1984, SIGPLAN '84.

[12]  Allen Newell,et al.  Computer Structures: Readings and Examples, , 1971 .

[13]  Christopher W. Fraser,et al.  The Design and Application of a Retargetable Peephole Optimizer , 1980, TOPL.

[14]  David W. Wall,et al.  The Mahler experience: using an intermediate language as the machine description , 1987, ASPLOS 1987.

[15]  Susan J. Eggers,et al.  Integrating register allocation and instruction scheduling for RISCs , 1991, ASPLOS IV.

[16]  Henry S. Warren,et al.  Instruction Scheduling for the IBM RISC System/6000 Processor , 1990, IBM J. Res. Dev..

[17]  M. Malik,et al.  Operating Systems , 1992, Lecture Notes in Computer Science.

[18]  Bruce D. Shriver,et al.  Local Microcode Compaction Techniques , 1980, CSUR.

[19]  Thomas R. Gross,et al.  Optimizing delayed branches , 1982, MICRO 15.

[20]  Alexandru Nicolau,et al.  Parallel processing: a smart compiler and a dumb machine , 1984, SIGP.

[21]  Peter L. Bird,et al.  Code Generation and Instruction Scheduling for Pipelined Sisd Machines , 1987 .

[22]  Thomas R. Gross,et al.  Postpass Code Optimization of Pipeline Constraints , 1983, TOPL.

[23]  Gregory J. Chaitin,et al.  Register allocation and spilling via graph coloring , 2004, SIGP.