Deign of Low power Domino Logic Circuits

Sub-threshold leakage power is soon estimated to dominate the total power consumed by a CMOS circuit in deep submicron ( DSM ) technology. Circuit techniques aimed at lowering leakage currents are therefore highly popular. In this work, low power CMOS designs using dual threshold voltage ( dual-Vt ) domino logic are projected. Single threshold voltage ( single-Vt ), standard dual-Vt and modified dual-Vt domino logic circuits regarding power and speed are compared. These design styles are compared by performing detailed transistorlevel simulations on bench mark circuits using DSCH3 and Microwind3 CAD tool.

[1]  Shin'ichiro Mutoh,et al.  1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.

[2]  Larry Welch,et al.  Issues in the design of domino logic circuits , 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).

[3]  Naresh R. Shanbhag,et al.  Energy-efficient dynamic circuit design in the presence of crosstalk noise , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[4]  Shekhar Borkar,et al.  Obeying Moore's law beyond 0.18 micron [microprocessor design] , 2000, Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541).

[5]  Shekhar Borkar,et al.  Low power design challenges for the decade , 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

[6]  Avi Mendelson,et al.  Coming challenges in microarchitecture and architecture , 2001, Proc. IEEE.

[7]  Yuan Taur,et al.  Device scaling limits of Si MOSFETs and their application dependencies , 2001, Proc. IEEE.

[8]  V. Kursun,et al.  Domino logic with dynamic body biased keeper , 2002, Proceedings of the 28th European Solid-State Circuits Conference.

[9]  M. Bohr.  Nanotechnology goals and challenges for electronic applications , 2002 .

[10]  A. Alvandpour,et al.  High-performance and low-power challenges for sub-70 nm microprocessor circuits , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).