Transaction Level Power Modeling (TLPM) Methodology

Power consumption is key specification in electronic design. Evaluating power consumption at early phase of product life cycle is important to decrease the number of the expensive design iterations. A methodology is proposed in this paper for dynamic power estimation using Transaction Level Modeling (TLM). The methodology exploits the existing tools for RTL simulation, design synthesis and SystemC prototyping to provide fast and accurate power estimation using Transaction Level Power Modeling (TLPM). Commercial IP timer is used to validate and evaluate the proposed methodology. Different scenarios are exercised to cover the functionality of the timer. Experimental results show the accuracy and efficiency of the methodology. The error in power estimation is less than 1.7%. Power estimation on TLM achieves upto 7x speedup in simulation time as compared to RTL.