A Phase-Locked Loop With Injection-Locked Frequency Multiplier in 0.18-$\mu{\hbox{m}}$ CMOS for $V$ -Band Applications

In this paper, a novel CMOS phase-locked loop (PLL) integrated with an injection-locked frequency multiplier (ILFM) that generates the V-band output signal is proposed. Since the proposed ILFM can generate the fifth-order harmonic frequency of the voltage-controlled oscillator (VCO) output, the operational frequency of the VCO can be reduced to only one-fifth of the desired frequency. With the loop gain smaller than unity in the ILFM, the output frequency range of the proposed PLL is from 53.04 to 58.0 GHz. The PLL is designed and fabricated in 0.18-mum CMOS technology. The measured phase noises at 1- and 10-MHz offset from the carrier are -85.2 and -90.9 dBc/Hz, respectively. The reference spur level of -40.16 dBc is measured. The dc power dissipation of the fabricated PLL is 35.7 mW under a 1.8-V supply. It can be seen that the advantages of lower power dissipation and similar phase noise can be achieved in the proposed PLL structure. It is suitable for low-power and high-performance V-band applications.

[1]  Yanping Ding,et al.  A 50-GHz Phase-Locked Loop in 0.13-$\mu$ m CMOS , 2007, IEEE Journal of Solid-State Circuits.

[2]  W. Simburger,et al.  A high sensitivity static 2:1 frequency divider up to 19 GHz in 120 nm CMOS , 2002, 2002 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. Digest of Papers (Cat. No.02CH37280).

[3]  K.K. O,et al.  A power efficient 26-GHz 32:1 static frequency divider in 130-nm bulk CMOS , 2005, IEEE Microwave and Wireless Components Letters.

[4]  B. Razavi,et al.  A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-/spl mu/m CMOS technology , 2000, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

[5]  B.A. Floyd.  A 16–18.8-GHz Sub-Integer-N Frequency Synthesizer for 60-GHz Transceivers , 2008, IEEE Journal of Solid-State Circuits.

[6]  Ichihiko Toyoda,et al.  A novel injection-locked oscillator MMIC with combined ultrawide-band active combiner/divider and amplifiers , 1994 .

[7]  Ichihiko Toyoda,et al.  A novel, injection locked oscillator MMIC with combined ultra-wide-band active combiner/divider and amplifiers , 1994, Proceedings of 1994 IEEE Microwave and Millimeter-Wave Monolithic Circuits Symposium.

[8]  Hyung-Kyu Lim,et al.  A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL , 1997 .

[9]  A. Ismail,et al.  CMOS differential LC oscillator with suppressed up-converted flicker noise , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[10]  Shen-Iuan Liu,et al.  A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[11]  Chung-Yu Wu,et al.  Design and Analysis of CMOS Subharmonic Injection-Locked Frequency Triplers , 2008, IEEE Transactions on Microwave Theory and Techniques.

[12]  B. Gaucher,et al.  A Silicon 60-GHz Receiver and Transmitter Chipset for Broadband Communications , 2006, IEEE Journal of Solid-State Circuits.

[13]  H.-D. Wohlmuth,et al.  A high sensitivity static 2:1 frequency divider up to 27GHz in 120nm CMOS , 2002, Proceedings of the 28th European Solid-State Circuits Conference.

[14]  H.R. Rategh,et al.  A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver , 2000, IEEE Journal of Solid-State Circuits.

[15]  Xiangdong Zhang,et al.  A theoretical and experimental study of the noise behavior of subharmonically injection locked local oscillators , 1992 .

[16]  G. Gerosa,et al.  A wide-bandwidth low-voltage PLL for PowerPC microprocessors , 1995 .

[17]  B. Floyd,et al.  A silicon 60GHz receiver and transmitter chipset for broadband communications , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[18]  Jri Lee.  A 75-GHz PLL in 90-nm CMOS Technology , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[19]  Toshiya Mitomo,et al.  A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS , 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.

[20]  F. Svelto,et al.  Analysis and design of injection-locked LC dividers for quadrature generation , 2004, IEEE Journal of Solid-State Circuits.

[21]  T.A. Kwasniewski,et al.  A 40-GHz Frequency Divider in 90-nm CMOS Technology , 2006, 2006 IEEE North-East Workshop on Circuits and Systems.

[22]  Jri Lee,et al.  A 40-GHz frequency divider in 0.18-/spl mu/m CMOS technology , 2004, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

[23]  Masayuki Mizuno,et al.  A GHz MOS adaptive pipeline technique using MOS current-mode logic , 1996, IEEE J. Solid State Circuits.