Advances in variation-aware modeling, verification, and testing of analog ICs

This tutorial paper describes novel scalable, nonlinear/generic, and industrially-oriented approaches to perform variation-aware modeling, verification, fault simulation, and testing of analog/custom ICs. In the first section, Dimitri De Jonghe, Elie Maricau, and Georges Gielen present a new advance in extracting highly nonlinear, variation-aware behavioral models, through the use of data mining and a re-framing of the model-order reduction problem. In the next section, Trent McConaghy describes new statistical machine learning techniques that enable new classes of industrial EDA tools, which in turn are enabling designers to perform fast and accurate PVT / statistical / high-sigma design and verification. In the third section, Bratislav Tasić presents a novel industrially-oriented approach to analog fault simulation that also has applicability to variation-aware design. In the final section, Haralampos Stratigopoulos describes describes state-of-the-art analog testing approaches that address process variability.

[1]  B. Gustavsen,et al.  Improving the pole relocating properties of vector fitting , 2006, 2006 IEEE Power Engineering Society General Meeting.

[2]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について - シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について - , 2004 .

[3]  Salvador Mir,et al.  Adaptive Alternate Analog Test , 2011, IEEE Design & Test of Computers.

[4]  Donald R. Jones,et al.  Efficient Global Optimization of Expensive Black-Box Functions , 1998, J. Glob. Optim..

[5]  Yang Zhong,et al.  Implementation of Defect Oriented Testing and ICCQ testing for industrial mixed-signal IC , 2007, 16th Asian Test Symposium (ATS 2007).

[6]  Mingjing Chen,et al.  Test cost minimization through adaptive test development , 2008, 2008 IEEE International Conference on Computer Design.

[7]  Trent McConaghy,et al.  High-dimensional statistical modeling and analysis of custom integrated circuits (invited paper) , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[8]  Abhijit Chatterjee,et al.  Signature Testing of Analog and RF Circuits: Algorithms and Methodology , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[9]  Liang-Hung Lu,et al.  A Build-in Self-Test Technique for RF Low-Noise Amplifiers , 2008, IEEE Transactions on Microwave Theory and Techniques.

[10]  A. Bowman An alternative method of cross-validation for the smoothing of density estimates , 1984 .

[11]  Gloria Huertas,et al.  Testing Mixed-Signal Cores: A Practical Oscillation-Based Test in an Analog Macrocell , 2002, IEEE Des. Test Comput..

[12]  I. Sloan,et al.  Low discrepancy sequences in high dimensions: How well are their projections distributed? , 2008 .

[13]  Georges Gielen,et al.  Compact trajectory-based behavioural models for analogue circuits , 2010 .

[14]  Scott Benner,et al.  Optimal production test times through adaptive test programming , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[15]  Rob A. Rutenbar,et al.  Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs , 2007, Proceedings of the IEEE.

[16]  Georges G. E. Gielen,et al.  Efficient analytical macromodeling of large analog circuits by Transfer Function Trajectories , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[17]  J. Freidman,et al.  Multivariate adaptive regression splines , 1991 .

[18]  Abhijit Chatterjee,et al.  Concurrent transient fault simulation for analog circuits , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Salvador Mir,et al.  RF Front-End Test Using Built-in Sensors , 2011, IEEE Design & Test of Computers.

[20]  Luca Daniel,et al.  Stable Reduced Models for Nonlinear Descriptor Systems Through Piecewise-Linear Approximation and Projection , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  Alberto Valdes-Garcia,et al.  On-Chip Testing Techniques for RF Wireless Transceivers , 2006, IEEE Design & Test of Computers.

[22]  Yiorgos Makris,et al.  Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[23]  Gordon W. Roberts,et al.  A 4-GHz effective sample rate integrated test core for analog and mixed-signal circuits , 2002, IEEE J. Solid State Circuits.

[24]  Yann Deval,et al.  Design of a 0.9 V 2.45 GHz Self-Testable and Reliability-Enhanced CMOS LNA , 2008, IEEE Journal of Solid-State Circuits.

[25]  Rajiv V. Joshi,et al.  Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[26]  Rob A. Rutenbar,et al.  Faster, parametric trajectory-based macromodels via localized linear reductions , 2006, ICCAD.

[27]  J. Silva-Martinez,et al.  An Integrated Frequency Response Characterization System With a Digital Interface for Analog Testing , 2006, IEEE Journal of Solid-State Circuits.

[28]  Rob A. Rutenbar,et al.  Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[29]  Frank Poehl,et al.  Production test challenges for highly integrated mobile phone SOCs — A case study , 2010, 2010 15th IEEE European Test Symposium.

[30]  Camelia Hora,et al.  Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example , 2011, 2011 Design, Automation & Test in Europe.

[31]  Camelia Hora,et al.  Defect Oriented Testing for analog/mixed-signal devices , 2011, 2011 IEEE International Test Conference.

[32]  M. Zwolinski,et al.  Fast, robust DC and transient fault simulation for nonlinear analogue circuits , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[33]  Sule Ozev,et al.  Adaptive test elimination for analog/RF circuits , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[34]  Yizi Xing,et al.  Cost Effective Outliers Screening with Moving Limits and Correlation Testing for Analogue ICs , 2006, 2006 IEEE International Test Conference.

[35]  Johan A. K. Suykens,et al.  Least Squares Support Vector Machine Classifiers , 1999, Neural Processing Letters.