Techniques for area estimation of VLSI layouts

The standard cell design style is investigated. Two probabilistic models are presented. The first model estimates the wiring space requirements in the routing channels between the cell rows. The second model estimates the number of feedthroughs that must be inserted in the cell rows to interconnect cells placed several rows apart. These models were implemented in the standard cell area estimation program PLEST (PLotting ESTimator). PLEST was used to estimate the areas of a set of 12 standard cell chips. In all cases, the estimates were accurate to within 10% of the actual areas. PLEST's estimation of a chip layout area takes only a few seconds to produce, as compared with more than 10 h to generate the chip layout itself using an industrial layout system. >

[1]  Nohbyung Park,et al.  Synthesis of High-Speed Digital Systems. , 1985 .

[2]  William R. Heller,et al.  Prediction of wiring space requirements for LSI , 1977, DAC '77.

[3]  Bill D. Richard.  A Standard Cell Initial Placement Strategy , 1984, 21st Design Automation Conference Proceedings.

[4]  Ernst G. Ulrich,et al.  Clustering and linear placement , 1972, DAC '72.

[5]  A. Feller,et al.  A speed oriented fully automatic layout program for random logic VLSI devices , 1978, AFIPS National Computer Conference.

[6]  Ikuo Harada,et al.  CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Kenneth J. Supowit.  Reducing Channel Density in Standard Cell Layout , 1983, 20th Design Automation Conference Proceedings.

[8]  Sungho Kang,et al.  Linear Ordering and Application to Placement , 1983, 20th Design Automation Conference Proceedings.

[9]  Alice C. Parker,et al.  A Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital Logic , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Roy L. Russo,et al.  On a Pin Versus Block Relationship For Partitions of Logic Graphs , 1971, IEEE Transactions on Computers.

[11]  Michael Feuer.  Connectivity of Random Logic , 1982, IEEE Transactions on Computers.

[12]  John J. Granacki,et al.  The Effect of Register-Transfer Design Tradeoffs on Chip Area and Performance , 1983, 20th Design Automation Conference Proceedings.

[13]  Abbas El Gamal,et al.  Two-dimensional stochastic model for interconnections in master-slice integrated circuits , 1981 .