An architecture of high-performance frequency and phase synthesis
暂无分享,去创建一个
[1] H. Eisenson. Frequency Synthesis Using DDS/NCO Technology , 1991, Electro International, 1991.
[2] F. Gardner,et al. Charge-Pump Phase-Lock Loops , 1980, IEEE Trans. Commun..
[3] P. Larsson. A 2-1600 MHz 1.2-2.5 V CMOS clock-recovery PLL with feedback phase-selection and averaging phase-interpolation for jitter reduction , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).
[4] Roland E. Best. Phase-Locked Loops , 1984 .
[5] M. Perez,et al. A contribution to DECT in frequency synthesis and modulation using DDS , 1993, IEEE 43rd Vehicular Technology Conference.
[6] M. Horowitz,et al. Precise delay generation using coupled oscillators , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[7] T. Riley,et al. Delta-sigma modulation in fractional-N frequency synthesis , 1993 .
[8] Paul R. Gray,et al. A 30-MHz hybrid analog/digital clock recovery circuit in 2- mu m CMOS , 1990 .
[9] D. P. Noel,et al. Frequency synthesis: a comparison of techniques , 1994, 1994 Proceedings of Canadian Conference on Electrical and Computer Engineering.
[10] Maher Rizkalla,et al. Maximizing the stability region for a second order PLL system , 1994, Proceedings of 1994 37th Midwest Symposium on Circuits and Systems.