To split or to group: from divide-and-conquer to sub-task sharing for verifying multiple properties in model checking
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Gianpiero Cabodi | Stefano Quer | Denis Patti | Paolo Camurati | Paolo Pasini | Marco Palena | Carmelo Loiacono
[1] Prabhat Mishra,et al. Functional Test Generation Using Efficient Property Clustering and Learning Techniques , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[2] Zurab Khasidashvili,et al. Simultaneous SAT-Based Model Checking of Safety Properties , 2005, Haifa Verification Conference.
[3] Shahid Ikram,et al. Accelerated verification of RTL assertions based on satisfiability solvers , 2002, Seventh IEEE International High-Level Design Validation and Test Workshop, 2002..
[4] Armin Biere. The AIGER And-Inverter Graph (AIG) Format Version 20070427 , 2007 .
[5] Robert P. Kurshan,et al. A Practical Approach to Coverage in Model Checking , 2001, CAV.
[6] Orna Kupferman,et al. Coverage metrics for temporal logic model checking* , 2006, Formal Methods Syst. Des..
[7] Fabio Somenzi,et al. Vacuum Cleaning CTL Formulae , 2002, CAV.
[8] Gianpiero Cabodi,et al. A graph‐labeling approach for efficient cone‐of‐influence computation in model‐checking problems with multiple properties , 2016, Softw. Pract. Exp..
[9] Edo Liberty,et al. Estimating Sizes of Social Networks via Biased Sampling , 2014, Internet Math..
[10] Timothy Kam,et al. Coverage estimation for symbolic model checking , 1999, DAC '99.
[11] Niklas Eén,et al. SAT Based Model Checking , 2005 .
[12] Kenneth L. McMillan,et al. Interpolation and SAT-Based Model Checking , 2003, CAV.
[13] Robert K. Brayton,et al. ABC: An Academic Industrial-Strength Verification Tool , 2010, CAV.
[14] Aaron R. Bradley,et al. SAT-Based Model Checking without Unrolling , 2011, VMCAI.
[15] Fabio Somenzi,et al. Dos and don'ts of CTL state coverage estimation , 2003, DAC '03.
[16] Gianpiero Cabodi,et al. Benchmarking a model checker for algorithmic improvements and tuning for performance , 2011, Formal Methods Syst. Des..
[17] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[18] Masahiro Fujita,et al. Symbolic model checking using SAT procedures instead of BDDs , 1999, DAC '99.
[19] Armin Biere,et al. Hardware model checking competition 2017 , 2017, 2017 Formal Methods in Computer Aided Design (FMCAD).
[20] Ilan Beer,et al. Efficient Detection of Vacuity in Temporal Model Checking , 2001, Formal Methods Syst. Des..
[21] Mingsong Chen,et al. Synchronized Generation of Directed Tests Using Satisfiability Solving , 2010, 2010 23rd International Conference on VLSI Design.
[22] A. Jefferson Offutt,et al. Mutation 2000: uniting the orthogonal , 2001 .
[23] Gianpiero Cabodi,et al. Optimized model checking of multiple properties , 2011, 2011 Design, Automation & Test in Europe.
[24] Marco Roveri,et al. The nuXmv Symbolic Model Checker , 2014, CAV.
[25] Hussain Al-Asaad,et al. A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[26] Armin Biere,et al. Hardware Model Checking Competition 2014: An Analysis and Comparison of Solvers and Benchmarks , 2014, J. Satisf. Boolean Model. Comput..
[27] Stefano Quer,et al. Fast Cone-Of-Influence computation and estimation in problems with multiple properties , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[28] Stefano Quer,et al. To split or to group: from divide-and-conquer to sub-task sharing in verifying multiple properties , 2014 .