Hybrid Mapping for Increased Security

In this chapter, it is shown that the introduced hybrid application mapping can also be utilized to increase security in heterogeneous many-core systems. In the case of security, it is proposed to use the concept of spatial isolation enabled by invasion to close side channels. This requires a shift from the optimization criteria in the previous chapter. There, the hop distance between tasks is maximized to increase the run-time embeddability as one constraint graph typically allows for many concrete mappings. For spatial isolation, so-called shapes as a second intermediate representation besides the constraint graph are introduced. As these shapes represent tiles and adjacent routers, no communication constraints have to be evaluated during run-time mapping. This eases the run-time mapping and transforms it basically to a constrained 2D packing problem. Consequently, fast heuristics as well as SAT-based solvers which choose fitting shape incarnations from each application concurrently may be applied.

[1]  Felix C. Freiling,et al.  Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs , 2016, SCOPES.

[2]  Radu Marculescu,et al.  Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Hermann Härtig,et al.  TETRiS: a Multi-Application Run-Time System for Predictable Execution of Static Mappings , 2017, SCOPES.

[4]  Wei Quan,et al.  A Hybrid Task Mapping Algorithm for Heterogeneous MPSoCs , 2015, ACM Trans. Embed. Comput. Syst..

[5]  Jürgen Teich,et al.  Hardware Supported Adaptive Data Collection for Networks on Chip , 2013, 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum.

[6]  Onur Aciiçmez,et al.  Yet another MicroArchitectural Attack:: exploiting I-Cache , 2007, CSAW '07.

[7]  Ran Ginosar,et al.  QNoC: QoS architecture and design process for network on chip , 2004, J. Syst. Archit..

[8]  Jürgen Teich,et al.  Optimization of Dynamic Hardware Reconfigurations , 2004, The Journal of Supercomputing.

[9]  Srdjan Capkun,et al.  Thermal Covert Channels on Multi-core Platforms , 2015, USENIX Security Symposium.

[10]  G. Edward Suh,et al.  Efficient Timing Channel Protection for On-Chip Networks , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

[11]  Paul C. Kocher,et al.  Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems , 1996, CRYPTO.

[12]  Srdjan Capkun,et al.  Isolated Execution on Many-core Architectures , 2014, IACR Cryptol. ePrint Arch..

[13]  Jürgen Teich,et al.  Task scheduling for heterogeneous reconfigurable computers , 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).

[14]  J. Jacob,et al.  Basic Theorems About Security , 1992, J. Comput. Secur..

[15]  S. K. Nandy,et al.  Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat , 2015, Circuits Syst. Signal Process..

[16]  Martin Lukasiewycz,et al.  Opt4J: a modular framework for meta-heuristic optimization , 2011, GECCO '11.

[17]  Majid Sarrafzadeh,et al.  Fast Template Placement for Reconfigurable Computing Systems , 2000, IEEE Des. Test Comput..

[18]  Vincenzo Catania,et al.  A methodology for design of application specific deadlock-free routing algorithms for NoC systems , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

[19]  Heba Khdr,et al.  Dark silicon management: an integrated and coordinated cross-layer approach , 2016, it Inf. Technol..

[20]  Jürgen Teich,et al.  Compile-time Optimization of Dynamic Hardware Reconfigurations , 1999, PDPTA.

[21]  Richard A. Kemmerer,et al.  Shared resource matrix methodology: an approach to identifying storage and timing channels , 1983, TOCS.

[22]  Guy Gogniat,et al.  NOC-centric Security of Reconfigurable SoC , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[23]  Christina Zamfirescu,et al.  Hamiltonian Properties of Grid Graphs , 1992, SIAM J. Discret. Math..

[24]  Felix C. Freiling,et al.  Providing security on demand using invasive computing , 2016, it Inf. Technol..

[25]  Michael Glaß,et al.  Towards scalable symbolic routing for multi-objective networked embedded system design and optimization , 2014, 2014 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[26]  Butler W. Lampson,et al.  A note on the confinement problem , 1973, CACM.

[27]  Daniel Le Berre,et al.  The Sat4j library, release 2.2 , 2010, J. Satisf. Boolean Model. Comput..

[28]  Jürgen Teich,et al.  Virtual networks -- distributed communication resource management , 2013, TRETS.

[29]  Amit Kumar Singh,et al.  Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs , 2013, TODE.