Easily testable realizations for generalized Reed-Muller expressions

This paper presents a design method of easily testable AND-EXOR networks. It is an improvement of Reddy and Saluja-Reddy's methods, and has the following features: 1) The network consists of a literal part, an AND part, an EXOR part, and a check part; 2) The EXOR part can be a tree instead of a cascade. Thus, the network is faster; 3) The network uses generalized Reed-Muller expressions (GRMs) instead of Positive Polarity Reed-Muller expressions (PPRMs). The number of products for GRMs is, on the average, less than a half of that for PPRMs, and is less than that of sum-of-products expression (SOPs); 4) The test detects multiple stuck-at-faults under the assumption that the faults occur in at most one part, either the literal part, the AND part, the EXOR part, or the check part.<<ETX>>

[1]  Tsutomu Sasao.  EXMIN2: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued-input two-valued-output functions , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Jean-Pierre Deschamps,et al.  Discrete and switching functions , 1978 .

[3]  Marek A. Perkowski,et al.  Fast minimization of mixed-polarity AND/XOR canonical networks , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[4]  Hideo Fujiwara.  On Closedness and Test Complexity of Logic Circuits , 1981, IEEE Transactions on Computers.

[5]  S. M Reddy,et al.  Easily testable realizations for logic functions , 1973 .

[6]  David H. Green,et al.  Modern logic design , 1986 .

[7]  Mark G. Karpovsky,et al.  Fault Detection in Combinational Networks by Reed-Muller Transforms , 1989, IEEE Trans. Computers.

[8]  Tsutomu Sasao.  And-Exor Expressions and their Optimization , 1993 .

[9]  Tsutomu Sasao,et al.  On the complexity of mod-2l sum PLA's , 1990 .

[10]  Sudhakar M. Reddy,et al.  Fault Detecting Test Sets for Reed-Muller Canonic Networks , 1975, IEEE Transactions on Computers.

[11]  M. Perkowski,et al.  Canonical restricted mixed-polarity exclusive-OR sums of products and the efficient algorithm for their minimisation , 1993 .

[12]  John P. Hayes.  On Realizations of Boolean Functions Requiring a Minimal or Near-Minimal Number of Tests , 1971, IEEE Transactions on Computers.

[13]  藤原 秀雄,et al.  Logic testing and design for testability , 1985 .

[14]  Dhiraj K. Pradhan,et al.  Universal Test Sets for Multiple Fault Detection in AND-EXOR Arrays , 1978, IEEE Transactions on Computers.

[15]  Marek A. Perkowski,et al.  Fast exact and quasi-minimal minimization of highly testable fixed-polarity AND/XOR canonical networks , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[16]  SUDHAKAR M. REDDY,et al.  Easily Testable Realizations ror Logic Functions , 1972, IEEE Transactions on Computers.

[17]  Sharad C. Seth,et al.  Diagnosis of Faults in Linear Tree Networks , 1977, IEEE Transactions on Computers.