InFO (Wafer Level Integrated Fan-Out) Technology

A powerful integrated fan-out (InFO) wafer level system integration (WLSI) technology has been developed to integrate application processor chip with memory package for smart mobile devices. This novel InFO technology is the first high performance Fan-Out Wafer Level Package (FO_WLP) with multi-layer high density interconnects proposed to the industry. In this paper we present the detailed comparison of InFO packages on package (InFO_PoP) with several other previously proposed 3D package solutions. Result shows that InFO_PoP has more optimized overall results on system performance, leakage power and area (form factor) than others, to meet the ever-increasing system requirements of mobile computing. InFO technology has been successfully qualified on package level with robust component and board level reliability. It is also qualified at interconnect level with high electromigration resistance. With its high flexibility and strong capability of multi-chips integration for both homogeneous and heterogeneous sub-systems, InFO technology not only provides a system scaling solution but also complements the chip scaling and helps to sustain the Moore's Law for the smart mobile as well as internet of things (IoT) applications.

[1]  Electromigration measurements in thin-film IPD and eWLB interconnections , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[2]  C. C. Liu,et al.  High-performance inductors for integrated fan-out wafer level packaging (InFO-WLP) , 2013, 2013 Symposium on VLSI Technology.

[3]  G. Meng,et al.  Electromigration Simulation for Metal Lines , 2010 .

[4]  Jiwoo Pak,et al.  Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[5]  Chewn-Pu Jou,et al.  High-performance integrated fan-out wafer level packaging (InFO-WLP): Technology and system integration , 2012, 2012 International Electron Devices Meeting.

[6]  J. Black,et al.  Electromigration—A brief survey and some recent results , 1969 .

[7]  Seung Wook Yoon,et al.  TSV MEOL (Mid End of Line) and packaging technology of mobile 3D-IC stacking , 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

[8]  Mitsumasa Koyanagi,et al.  High-Density Through Silicon Vias for 3-D LSIs , 2009, Proceedings of the IEEE.

[9]  Said F. Al-Sarawi,et al.  A Review of 3-D Packaging Technology , 1998 .

[10]  Chung-Hao Tsai,et al.  Array antenna integrated fan-out wafer level packaging (InFO-WLP) for millimeter wave system applications , 2013, 2013 IEEE International Electron Devices Meeting.

[11]  Siegfried Selberherr,et al.  Physically based models of electromigration: From Black's equation to modern TCAD models , 2010, Microelectron. Reliab..

[12]  M. Brunnbauer,et al.  Embedded Wafer Level Ball Grid Array (eWLB) , 2008, 2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT).

[13]  Douglas Yu A new integration technology platform: Integrated fan-out wafer-level-packaging for mobile applications , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[14]  Doug C. H. Yu New System-in-Package (SiP) Integration technologies , 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

[15]  J.-C. Souriau,et al.  Wafer level processing of 3D system in package for RF and data application , 2005, Proceedings Electronic Components and Technology, 2005. ECTC '05..