A 90-nm CMOS 4 × 10 Gb/s VCSEL driver using asymmetric emphasis technique for optical interconnection

In this paper, a method for controlling the driving current is discussed and then an asymmetric emphasis technique that individually controls its waveform at the rising and falling edges is proposed. The circuit implementation for the asymmetric emphasis technique is discussed and experimental results for the fabricated test chip is provided.

[1]  Y. Kwark,et al.  Pre-Emphasis and Regulated Output Impedance in 0.13∝m CMOS , 2005 .

[2]  Frank Ellinger,et al.  Tradeoffs of vertical-cavity surface emitting lasers modeling for the development of driver circuits in short distance optical links , 2005 .

[3]  A. Chandrakasan,et al.  18Gb/s Optical IO: VCSEL Driver and TIA in 90nm CMOS , 2007, 2007 IEEE Symposium on VLSI Circuits.

[4]  Andrew C. Y. Lin,et al.  A Serial Data Transmitter for Multiple 10Gb/s Communication Standards in 0.13μm CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[5]  Y. Kwark,et al.  A 20 Gb/s VCSEL driver with pre-emphasis and regulated output impedance in 0.13 /spl mu/m CMOS , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[6]  S. Palermo,et al.  High-Speed Transmitters in 90nm CMOS for High-Density Optical Interconnects , 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.