IP Routing table compaction and sampling schemes to enhance TCAM cache performance

Routing table lookup is an important operation in packet forwarding. This operation has a significant influence on the overall performance of the network processors. Routing tables are usually stored in main memory which has a large access time. Consequently, small fast cache memories are used to improve access time. In this paper, we propose a novel routing table compaction scheme to reduce the number of entries in the routing table. The proposed scheme has three versions. This scheme takes advantage of ternary content addressable memory (TCAM) features. Two or more routing entries are compacted into one using don't care elements in TCAM. A small compacted routing table helps to increase cache hit rate; this in turn provides fast address lookups. We have evaluated this compaction scheme through extensive simulations involving IPv4 and IPv6 routing tables and routing traces. The original routing tables have been compacted over 60% of their original sizes. The average cache hit rate has improved by up to 15% over the original tables. We have also analyzed port errors caused by caching, and developed a new sampling technique to alleviate this problem. The simulations show that sampling is an effective scheme in port error-control without degrading cache performance.

[1]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[2]  George Varghese,et al.  Faster IP lookups using controlled prefix expansion , 1998, SIGMETRICS '98/PERFORMANCE '98.

[3]  Christian Huitema,et al.  IPv6--the new Internet protocol , 1996 .

[4]  José G. Delgado-Frias,et al.  A high-performance encoder with priority lookahead , 2000 .

[5]  Stephen E. Deering,et al.  IP Version 6 Addressing Architecture , 1995, RFC.

[6]  Hung-Hsiang Jonathan Chao,et al.  Next generation routers , 2002, Proc. IEEE.

[7]  D. C. Feldmeier,et al.  Improving gateway performance with a routing-table cache , 1988, IEEE INFOCOM '88,Seventh Annual Joint Conference of the IEEE Computer and Communcations Societies. Networks: Evolution or Revolution?.

[8]  Huan Liu,et al.  Routing prefix caching in network processor design , 2001, Proceedings Tenth International Conference on Computer Communications and Networks (Cat. No.01EX495).

[9]  Tzi-cker Chiueh,et al.  Cache memory design for network processors , 2000, Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550).

[10]  David A. Patterson,et al.  Computer Architecture - A Quantitative Approach, 5th Edition , 1996 .

[11]  V. Srinivasan,et al.  Fast address lookups using controlled prefix expansion , 1999, TOCS.

[12]  Kwan Lawrence Yeung,et al.  Efficient hardware architecture for fast IP address lookup , 2002, Proceedings.Twenty-First Annual Joint Conference of the IEEE Computer and Communications Societies.

[13]  Bernhard Plattner,et al.  Scalable high-speed prefix matching , 2001, TOCS.

[14]  Huan Liu.  Routing Table Compaction in Ternary CAM , 2002, IEEE Micro.

[15]  Bill Lin,et al.  IP caching for terabit speed routers , 1999, Seamless Interconnection for Universal Services. Global Telecommunications Conference. GLOBECOM'99. (Cat. No.99CH37042).

[16]  Stephan Wong,et al.  Cache replacement policies for IP address lookups , 2007 .

[17]  Nian-Feng Tzeng.  Routing table partitioning for speedy packet lookups in scalable routers , 2006, IEEE Transactions on Parallel and Distributed Systems.

[18]  José G. Delgado-Frias,et al.  Associative ternary cache for IP routing , 2004 .

[19]  Gunnar Karlsson,et al.  IP-address lookup using LC-tries , 1999, IEEE J. Sel. Areas Commun..

[20]  Nick McKeown,et al.  Routing lookups in hardware at memory access speeds , 1998, Proceedings. IEEE INFOCOM '98, the Conference on Computer Communications. Seventeenth Annual Joint Conference of the IEEE Computer and Communications Societies. Gateway to the 21st Century (Cat. No.98.

[21]  José G. Delgado-Frias,et al.  Decoupled dynamic ternary content addressable memories , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.