Improving the energy efficiency of a low-area SATD hardware architecture using fine grain PDE

Video coding has become widespread through mobile devices. At the same time, the adopted resolutions have been enlarged, demanding more coding efficiency and motivating the development of the new state-of-the-art standard, High Efficiency Video Coding (HEVC). However, to achieve the required efficiency the new standard greatly increased the computational intensity. That, allied to real-time constraints on mobile devices, results in a need for dedicated hardware implementations. A large part of the increasing complexity came at the Motion Estimation (ME) in the prediction coding step using larger blocks and more candidates. In ME, similarity metrics are a centerpiece of the performance achieved, both on coding efficiency and required computations. Among the used metrics is the Sum of Absolute Transformed Differences (SATD). Such metric may be calculated using a Transpose Buffer (TB) which largely increases the architecture area as block sizes increase. Alternatively, a Linear Buffer (LB) can be used, which results in less area at the cost of more energy consumption. This paper evaluates the use of Partial Distortion Elimination (PDE) as a means to reduce the energy consumption penalty associated with LB architectures. Our experimental results show that using PDE along with the LB architecture provides up to 65.61% energy reduction while negligibly degrading area.