ReCoNet: modeling and implementation of fault tolerant distributed reconfigurable hardware

Recent research was mainly focused on the OS support for a single reconfigurable chip. This paper presents a general approach to manage fault tolerant distributed reconfigurable hardware. In order to run such a system, three basic tasks must be implemented: (i) rerouting to compensate line errors, (ii) rebinding to compensate node failures, and (iii) hardware reconfiguration to allow the optimization of these systems during runtime. This paper proposes first ideas and solutions of these management functions. Furthermore, a prototype implementation consisting of four fully connected FPGAs is presented.

[1]  Ranga Vemuri,et al.  An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures , 1998, IPPS/SPDP Workshops.

[2]  Jürgen Teich,et al.  Optimal FPGA module placement with temporal precedence constraints , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[3]  Andrew S. Tanenbaum,et al.  Computer Networks , 1981 .

[4]  Marco Platzner,et al.  Online scheduling for block-partitioned reconfigurable devices , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[5]  N.K. Jha,et al.  CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[6]  Jürgen Teich,et al.  System-Level Synthesis Using Evolutionary Algorithms , 1998, Des. Autom. Embed. Syst..

[7]  G. Constantinides,et al.  Fault Tolerance Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques ? , 2003 .

[8]  V. Baumgarte,et al.  PACT XPP-A Self-Reconfigurable Data Processing Architecture , 2001 .

[9]  Hermann Kopetz,et al.  Real-time systems , 2018, CSC '73.

[10]  T. Dumitras,et al.  Towards on-chip fault-tolerant communication , 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

[11]  Markus Weinhardt,et al.  PACT XPP—A Self-Reconfigurable Data Processing Architecture , 2003, The Journal of Supercomputing.