Semiconductor memory device having fail address programming circuit and fail address programming circuit thereof

A semiconductor memory device having a defective address program circuit, and it is disclosed. Defective address programming circuit according to an embodiment of the present invention includes the first to n-th latch portion and the first to n-th programming cells. The first to n-th latch unit stores the defective address signal of m bits 1 to n in response to the selection signal having information about the position of the defective cell of the semiconductor memory device. First to n-th programming cell is receiving the defective address signal from the first to n-th latch unit, in response to a programming signal and performs the programming corresponding to the defective address signal. The first to n-th cell is programmed at the same time performs the programming in response to said programming signal. Defective address program circuit and a semiconductor memory device according to the invention can advantageously reduce the time to program a defective address signal. Therefore, the defect redundancy operation speed is faster, the advantages of the semiconductor memory device.