Software-Based Self-Test of Set-Associative Cache Memories

Embedded microprocessor cache memories suffer from limited observability and controllability creating problems during in-system tests. This paper presents a procedure to transform traditional march tests into software-based self-test programs for set-associative cache memories with LRU replacement. Among all the different cache blocks in a microprocessor, testing instruction caches represents a major challenge due to limitations in two areas: 1) test patterns which must be composed of valid instruction opcodes and 2) test result observability: the results can only be observed through the results of executed instructions. For these reasons, the proposed methodology will concentrate on the implementation of test programs for instruction caches. The main contribution of this work lies in the possibility of applying state-of-the-art memory test algorithms to embedded cache memories without introducing any hardware or performance overheads and guaranteeing the detection of typical faults arising in nanometer CMOS technologies.

[1]  K. Roy,et al.  Modeling and estimation of failure probability due to parameter variations in nano-scale SRAMs for yield enhancement , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[2]  Tariq Jamil,et al.  Cache memories , 2000 .

[3]  Bruce Jacob,et al.  Memory Systems: Cache, DRAM, Disk , 2007 .

[4]  A.J. van de Goor,et al.  Functional testing of modern microprocessors , 1992, [1992] Proceedings The European Conference on Design Automation.

[5]  Georgi Gaydadjiev,et al.  March U: a test for unlinked memory faults , 1997 .

[6]  Wen-Ben Jone,et al.  Fault Modeling and Detection for Drowsy SRAM Caches , 2006, 2006 IEEE International Test Conference.

[7]  Said Hamdioui,et al.  Linked faults in random access memories: concept, fault models, test algorithms, and industrial results , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Dimitris Gizopoulos,et al.  Software-based self-testing of embedded processors , 2005, IEEE Transactions on Computers.

[9]  Yervant Zorian,et al.  Embedded Processor-Based Self-Test , 2004 .

[10]  Mihalis Psarakis,et al.  Software-Based Self-Testing of Symmetric Shared-Memory Multiprocessors , 2009, IEEE Transactions on Computers.

[11]  Janusz Sosnowski.  In-system testing of cache memories , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[12]  Jaime Velasco-Medina,et al.  Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs , 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

[13]  Alfredo Benso,et al.  Specification and design of a new memory fault simulator , 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

[14]  Sujit Dey,et al.  Embedded Software-Based Self-Test for Programmable Core-Based Designs , 2002, IEEE Des. Test Comput..

[15]  Kaushik Roy,et al.  A high performance IDDQ testable cache for scaled CMOS technologies , 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

[16]  Alessandro Savino,et al.  Applying March Tests to K-Way Set-Associative Cache Memories , 2008, 2008 13th European Test Symposium.

[17]  Sandeep K. Gupta,et al.  A methodology for transforming memory tests for in-system testing of direct mapped cache tags , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[18]  Dilip K. Bhavsar,et al.  Testability strategy of the Alpha AXP 21164 microprocessor , 1994, Proceedings., International Test Conference.

[19]  Dileep Bhandarkar,et al.  Performance characterization of the Pentium Pro processor , 1997, Proceedings Third International Symposium on High-Performance Computer Architecture.

[20]  Yervant Zoriaii.  Effective March Algorithms for Testing Single-Order Addressed Memories , 1993 .

[21]  Paolo Prinetto,et al.  Models in Memory Testing , 2010 .

[22]  J. Sosnowski,et al.  Improving Software Based Self - Testing for Cache Memories , 2007, 2007 2nd International Design and Test Workshop.

[23]  Robert F. Molyneaux,et al.  Random self-test method applications on PowerPC/sup TM/ microprocessor caches , 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).

[24]  Tung Le,et al.  Testing of UltraSPARC T1 Microprocessor and its Challenges , 2006, 2006 IEEE International Test Conference.

[25]  W. Paul,et al.  Computer Architecture , 2000, Springer Berlin Heidelberg.

[26]  Said Hamdioui,et al.  March SS: a test for all static simple RAM faults , 2002, Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002).

[27]  Said Hamdioui,et al.  Testing static and dynamic faults in random access memories , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[28]  Kaushik Roy,et al.  A process-tolerant cache architecture for improved yield in nanoscale technologies , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[29]  Sujit Dey,et al.  A scalable software-based self-test methodology for programmable processors , 2003, DAC '03.

[30]  A. J. van de Goor,et al.  Testing Semiconductor Memories: Theory and Practice , 1998 .

[31]  Ad J. van de Goor,et al.  A Systematic Method for Modifying March Tests for Bit-Oriented Memories into Tests for Word-Oriented Memories , 2003, IEEE Trans. Computers.

[32]  Alfredo Benso,et al.  March Test Generation Revealed , 2008, IEEE Transactions on Computers.

[33]  A. Benso,et al.  An on-line software-based self-test framework for microprocessor cores , 2006, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006..

[34]  Matteo Sonza Reorda,et al.  A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs , 2008, 2008 14th IEEE International On-Line Testing Symposium.

[35]  Ad J. van de Goor,et al.  Using March Tests to Test SRAMs , 1993, IEEE Des. Test Comput..

[36]  Dirk Grunwald,et al.  Pipeline gating: speculation control for energy reduction , 1998, ISCA.

[37]  Janusz Sosnowski.  Software-based self-testing of microprocessors , 2006, J. Syst. Archit..