TIES: A testability increase expert system for VLSI design

TIES is a knowledge based system that advises the ICs designer on the best modifications to perform on a circuit with testability problems, while satisfying design constraints defined by the user. The proposed approach differs from previous papers for three main reasons. The DfT techniques are applied only to critical areas of the circuit which are identified by means of a testability measure. A powerful description of design for testability techniques in the knowledge base is adopted. Moreover, a new decision scheme for the comparison among different implementations is proposed.

[1]  Kyushik Son.  Rule Based Testability Checker and Test Generator , 1985, ITC.

[2]  Donatella Sciuto,et al.  ALADIN: a multilevel testability analyzer for VLSI system design , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Magdy Abadir,et al.  A Knowledge-Based System for Designing Testable VLSI Chips , 1985, IEEE Design & Test of Computers.

[4]  Paolo Prinetto,et al.  ESTA: an expert system for DFT rule verification , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Ralph H. J. M. Otten,et al.  Tackling cost optimization in testable design by forward inferencing , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

[6]  Anthony P. Ambler,et al.  Economic effects in design and test , 1991, IEEE Design & Test of Computers.

[7]  Parimal Pal Chaudhuri,et al.  Expert system to configure global design for testability structure in a VLSI circuit , 1989, Microprocess. Microsystems.

[8]  Daniel G. Saab,et al.  Beta: behavioral testability analysis , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[9]  D. G. Saab,et al.  Structural and behavioral synthesis for testability techniques , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  M.S. Abadir.  TIGER: testability insertion guidance expert system , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[11]  Melvin A. Breuer,et al.  Reorganizing circuits to aid testability , 1991, IEEE Design & Test of Computers.

[12]  Franco Fummi,et al.  An approach to a design for testability personal consultant , 1990 .

[13]  Melvin A. Breuer,et al.  Synthesis of optimal 1-hot coded on-chip controllers for BIST hardware , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[14]  Melvin A. Breuer,et al.  A systematic approach for designing testable VLSI circuits , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[15]  Melvin A. Breuer,et al.  SIESTA: a multi-facet scan design system , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.