Reduced memory architecture for CORDIC-based FFT

In this paper, a new pipelined, reduced memory CORDIC-based architecture is presented for any radix size FFT. A multi-bank memory structure and the corresponding addressing scheme are used to realize the parallel and in-place data accesses. The proposed memory-reduced CORDIC algorithm eliminates the need for storing twiddle factors and angles, resulting in significant area savings with no negative impact on performance. As a case study, the radix-2 and radix-4 FFT algorithms have been implemented on FPGA hardware. The synthesis results match the theoretical analysis and it can be observed that more than 20% reduction can be achieved in total memory logic.

[1]  Jack E. Volder.  The CORDIC Trigonometric Computing Technique , 1959, IRE Trans. Electron. Comput..

[2]  Jesús Grajal,et al.  Efficient Memoryless Cordic for FFT Computation , 2007, 2007 IEEE International Conference on Acoustics, Speech and Signal Processing - ICASSP '07.

[3]  Chin-Long Wey,et al.  Efficient memory-based FFT processors for OFDM applications , 2007, 2007 IEEE International Conference on Electro/Information Technology.

[4]  Jayshankar.  Efficient computation of the DFT of a 2N - point real sequence using FFT with CORDIC based butterflies , 2008, TENCON 2008 - 2008 IEEE Region 10 Conference.

[5]  Yutai Ma,et al.  An effective memory addressing scheme for FFT processors , 1999, IEEE Trans. Signal Process..

[6]  M.B. Srinivas,et al.  On the suitability of Bruun’s FFT algorithm for software defined radio , 2007, 2007 IEEE Sarnoff Symposium.

[7]  Erdal Oruklu,et al.  Fast memory addressing scheme for radix-4 FFT implementation , 2009, 2009 IEEE International Conference on Electro/Information Technology.

[8]  Luca Fanucci,et al.  Single-chip mixed-radix FFT processor for real-time on-board SAR processing , 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

[9]  Erdal Oruklu,et al.  An Efficient FFT Engine With Reduced Addressing Logic , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.