Effect of tensile capping layer on 3-D stress profiles in FinFET channels

Strained-silicon technologies have been widely investigated to enhance the performance of CMOS devices (Thompson, et. al., 2005). In particular, strain induced by the use of a stressed SiNx capping layer is advantageous because of its process simplicity and its extendibility from bulk-Si to silicon-on-insulator (SOI) MOSFETs (Komoda, 2004, Pidin, 2004). In this paper, the effect of a tensile capping layer on the stress profile in the channel of a FinFET is studied for different channel-surface crystalline orientations and different fin aspect ratios, using the Ansys5.7 simulator

[1]  R. Chau,et al.  In search of "Forever," continued transistor scaling one new material at a time , 2005, IEEE Transactions on Semiconductor Manufacturing.

[2]  Yuhao Luo,et al.  Enhancement of CMOS performance by process-induced stress , 2005, IEEE Transactions on Semiconductor Manufacturing.

[3]  C.C. Chen,et al.  Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[4]  Chenming Hu,et al.  Sub-60-nm quasi-planar FinFETs fabricated using a simplified process , 2001, IEEE Electron Device Letters.