论文信息 - On the design of power-rail esd clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process

On the design of power-rail esd clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process

A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with the consideration of gate-leakage issue is proposed and verified in a 65-nm low-voltage CMOS process. The new proposed design has a very small leakage current of only 228 nA at 25 °C in the silicon chip. Moreover, it can achieve ESD robustness of over 8kV in human-body-model (HBM) and 750V in machine-model (MM) ESD tests, respectively.

Ming-Dou Ker | Yeong-Jar Chang | Po-Yen Chiu | Fu-Yi Tsai

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