Eight Bit Serial Triangular Compressor Based Multiplier
暂无分享,去创建一个
[1] R. Gnanasekaran,et al. On a Bit-Serial Input and Bit-Serial Output Multiplier , 1983, IEEE Transactions on Computers.
[2] V. Thomas Rhyne,et al. A Canonical Bit-Sequential Multiplier , 1982, IEEE Transactions on Computers.
[3] Noel R. Strader,et al. A Signed Bit-Sequential Multiplier , 1986, IEEE Transactions on Computers.
[4] N. Kanopoulos. A bit-serial architecture for digital signal processing , 1985 .
[5] Tung-Sang Ng,et al. Efficient FPGA implementation of bit-stream multipliers , 2007 .
[6] R. Gnanasekaran,et al. A Fast Serial-Parallel Binary Multiplier , 1985, IEEE Transactions on Computers.
[7] Woon-Seng Gan,et al. Teaching DSP software development: from design to fixed-point implementations , 2006, IEEE Transactions on Education.
[8] Henk J. Sips. Comments on "An O(n) Parallel Multiplier with Bit-Sequential Input and Output" , 1982, IEEE Trans. Computers.
[9] Richard F. Lyon,et al. Two's Complement Pipeline Multipliers , 1976, IEEE Trans. Commun..
[10] Oscar Castillo,et al. Proceedings of the International MultiConference of Engineers and Computer Scientists 2007, IMECS 2007, March 21-23, 2007, Hong Kong, China , 2007, IMECS.
[11] Luigi Dadda,et al. On Serial-Input Multipliers for Two's Complement Numbers , 1989, IEEE Trans. Computers.
[12] Peter B. Denyer,et al. VLSI Signal Processing: A Bit-Serial Approach , 1985 .