An FPGA-Based Linear All-Digital Phase-Locked Loop

In this paper, an all-digital phase-locked loop (ADPLL) is presented, and it is implemented on a field-programmable gate array. All components like the phase detector (PD), oscillator, and loop filter are realized as digital discrete-time components fed from analog-to-digital converters. The phase detection is realized by generating first an analytic signal using a compact implementation of the Hilbert transform and then computing the instantaneous phase with the CORDIC algorithm. A phase-unwrap component was realized, which extends the linear range of the PD, so that the linear model is valid in the full frequency range. This property leads to a constant lock-in time for arbitrary frequency changes. An analytic solution for the lock-in frequency range and the stability range including processing delays is given. All relations to design an ADPLL of the presented structure are derived. A detailed example application of an ADPLL designed as an offset local oscillator is given.

[1]  E. Mokhtari,et al.  CMOS high-resolution all-digital phase-locked loop , 2003, 2003 46th Midwest Symposium on Circuits and Systems.

[2]  Won Namgoong.  Flicker Noise in Observer-Controller Digital PLL , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[3]  Floyd M. Gardner,et al.  Phaselock Techniques: Gardner/Phaselock Techniques , 2005 .

[4]  B. Gold,et al.  A digital frequency synthesizer , 1971 .

[5]  Kuei-Ann Wen,et al.  A Low-Power 2.4-GHz CMOS GFSK Transceiver With a Digital Demodulator Using Time-to-Digital Conversion , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  J. Stensby,et al.  An approximation of the pull-out frequency parameter in a second-order PLL , 2006, 2006 Proceeding of the Thirty-Eighth Southeastern Symposium on System Theory.

[7]  Uwe Meyer-Baese,et al.  Digital Signal Processing with Field Programmable Gate Arrays , 2001 .

[8]  Behrouz Farhang-Boroujeny,et al.  Parameter Derivation of Type-2 Discrete-Time Phase-Locked Loops Containing Feedback Delays , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[9]  Wei Wang,et al.  A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[10]  O.A. Mohamed,et al.  FPGA Implementation and Performance Evaluation of a Digital Carrier Synchronizer Using Different Numerically Controlled Oscillators , 2007, 2007 Canadian Conference on Electrical and Computer Engineering.

[11]  Pavan Kumar Hanumolu,et al.  A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[12]  S. Hahn.  Hilbert Transforms in Signal Processing , 1996 .

[13]  Y. Linn,et al.  A Methodical Approach to Hybrid PLL Design for High-Speed Wireless Communications , 2006, 2006 IEEE Annual Wireless and Microwave Technology Conference.

[14]  Venceslav F. Kroupa,et al.  Direct digital frequency synthesizers , 1998 .

[15]  Fuminori Kobayashi,et al.  A digital PLL with finite impulse responses , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[16]  Věnceslav F. Kroupa,et al.  Phase Lock Loops and Frequency Synthesis: Kroupa/Phase Lock Loops , 2005 .

[17]  Martin Kumm,et al.  Digital hilbert transformers for FPGA-based phase-locked loops , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[18]  K. A. Semendyayev,et al.  Handbook of mathematics , 1985 .

[19]  L. Musa.  FPGAS in high energy physics experiments at CERN , 2008, FPL.

[20]  Harald Klingbeil,et al.  A fast DSP-based phase-detector for closed-loop RF control in synchrotrons , 2005, IEEE Transactions on Instrumentation and Measurement.

[21]  J. Vuori.  Implementation of a digital phase-locked loop using CORDIC algorithm , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[22]  Won Namgoong.  Observer-Controller Digital PLL , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[23]  In-Joong Ha,et al.  Design of ADPLL for both large lock-in range and good tracking performance , 1999 .

[24]  Kwang-Hee Choi,et al.  An Interpolating Digitally Controlled Oscillator for a Wide-Range All-Digital PLL , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[25]  Jack E. Volder.  The CORDIC Trigonometric Computing Technique , 1959, IRE Trans. Electron. Comput..

[26]  Venceslav F. Kroupa,et al.  An Analysis of the Output Spectrum of Direct Digital Frequency Synthesizers in the Presence of PhaseAccumulator Truncation , 1999 .

[27]  H. Klingbeil,et al.  A Digital Beam-Phase Control System for Heavy-Ion Synchrotrons , 2007, IEEE Transactions on Nuclear Science.

[28]  Jen-Wei Hsieh,et al.  A novel ultra-high speed signal capture based on a single FPGA chip , 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

[29]  H. Samueli,et al.  An Analysis of the Output Spectrum of Direct Digital Frequency Synthesizers in the Presence of Phase-Accumulator Truncation , 1987, 41st Annual Symposium on Frequency Control.