Efficient Testing Of Clock Regenerator Circuits In Scan Designs

This paper describes the use of a high-level view (functional view) of a clock regenerator circuit for generating effective and inexpensive manufacturing tests. It is shown that the tests generated from the traditional, structural view add hardware overhead, increase design time and potentially lower effective yield when compared to the tests generated from the functional view. A test generation procedure is described and successfully used on a microprocessor design.