Performances of a Dynamic Threads Scheduler

This paper presents the design and development of a dynamic scheduler of parallel threads in the Multithreaded multiProcessor Architecture (MPA). The scheduler relies on an on-chip associative memory whose management time is overlapped with the execution of ready threads. The scheduler efficiently assigns resources to threads, and permits them to communicate with great flexibility. The results achieved with small number of threads from programs with high degree of parallelism are very satisfactory, even under various degrees of cache misses.