A simulation study of hardware-oriented DSM approaches
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[1] Veljko M. Milutinovic,et al. Hardware approaches to cache coherence in shared-memory multiprocessors. 2 , 1994, IEEE Micro.
[2] John L. Hennessy,et al. Evaluating the memory overhead required for COMA architectures , 1994, ISCA '94.
[3] Anoop Gupta,et al. The Stanford Dash multiprocessor , 1992, Computer.
[4] J. Rothnie,et al. The KSR 1: bridging the gap between shared memory and MPPs , 1993, Digest of Papers. Compcon Spring.
[5] J. K. Archibald. The cache coherence problem in shared-memory multiprocessors , 1987 .
[6] Veljko M. Milutinovic,et al. Hardware approaches to cache coherence in shared-memory multiprocessors, Part 1 , 1994, IEEE Micro.
[7] Erik Hagersten,et al. DDM - A Cache-Only Memory Architecture , 1992, Computer.
[8] James K. Archibald,et al. Cache coherence protocols: evaluation using a multiprocessor simulation model , 1986, TOCS.
[9] David B. Gustavson. The Scalable Coherent Interface and related standards projects , 1992, IEEE Micro.
[10] Veljko M. Milutinovic,et al. Distributed shared memory: concepts and systems , 1997, IEEE Parallel Distributed Technol. Syst. Appl..
[11] Anoop Gupta,et al. Comparative performance evaluation of cache-coherent NUMA and COMA architectures , 1992, ISCA '92.
[12] Veljko Milutinovic,et al. The Cache Coherence Problem in Shared-Memory Multiprocessors: Software Solutions , 1996 .
[13] J. L. Hennessy,et al. An empirical comparison of the Kendall Square Research KSR-1 and Stanford DASH multiprocessors , 1993, Supercomputing '93.