Hazard Algebra and the Design of Asynchronous Automata

Our concern is the design of provably correct asynchronous circuits. In such circuits there may occur hazards, due to the delay of signals along wires and components. Informally, a hazard is a time interval during which the output of a circuit, or circuit component, is wrong. Hazards are hardly ever defined formally in the literature. For a synchronous circuit designer this might be no problem as he assumes the outputs of all components are correct (and stabile) by the next clock edge. Asynchronous or clockless circuits may feature hazards, even though all components are correct. So it is of vital importance for the asynchronous system designer to be able to reason formally about hazards. We shall design an algebra, a formal system, for this purpose and we shall use it to design asynchronous finite-state machines. For reasons of space most of the proofs have been omitted. These will be included in an expanded version of this paper.

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