Design of a High-Performance Scalable CDMA Router for On-Chip Switched Networks

Performance results and synthesized area overhead for a code division multiple access (CDMA) router intended for network-on-chip (NoC) applications are presented. Specific architectural block diagrams of the main components of the router are given and synthesis results are provided for 0.18 micron and 0.25 micron structured ASIC libraries. Post-synthesis VHDL simulations verify the functionality of the router and provide values for packet transmission latency and throughput as functions of the payload size. The router can be used to construct star+star and star+mesh network architectures which can be scaled to meet the needs of high-performance applications.

[1]  Takafumi Aoki,et al.  An efficient data transmission technique for VLSI systems based on multiple-valued code-division multiple access , 2000, Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000).

[2]  Partha Pratim Pande,et al.  Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs , 2004, GLSVLSI '04.

[3]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[4]  T. Matsuoka,et al.  DS-CDMA wired bus with simple interconnection topology for parallel processing system LSIs , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[5]  Kuan Jen Lin,et al.  A Schedulable DMA Scheme for Real Time Systems , 2005 .

[6]  Dake Liu,et al.  Design of a system-on-chip switched network and its design support , 2002, IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions.

[7]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[8]  Luca Benini,et al.  Networks on chip: a new paradigm for systems on chip design , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[9]  Chang Yong Kang,et al.  CDMA as a multiprocessor interconnect strategy , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).

[10]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.