A 45–75MHz 197–452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS

This paper presents a novel oscillator architecture that uses a low frequency temperature stable clock generated by a low power RC relaxation oscillator to improve the temperature stability of a low noise ring oscillator. Fabricated in 65nm CMOS process, the prototype oscillator consumes 197 to 452µW across an output frequency range of 45-to-75MHz. At 70MHz, the measured period jitter is 2.3psrms with phase noise of −104dBc/Hz at 100kHz offset, which translates to an FoM of 164.6dB.

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