Interconnect delay testings of designs on programmable logic devices
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[1] Gabriel Robins,et al. New performance-driven FPGA routing algorithms , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[2] Hideo Fujiwara,et al. A test methodology for interconnect structures of LUT-based FPGAs , 1996, Proceedings of the Fifth Asian Test Symposium (ATS'96).
[3] Michel Renovell. Some Aspects of the Test Generation Problem for an Application-Oriented Test of SRAM-Based FPGAs , 2003, J. Circuits Syst. Comput..
[4] Fabrizio Lombardi,et al. A diagnosis method for interconnects in SRAM based FPGAs , 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).
[5] Charles E. Stroud,et al. BIST-Based Delay-Fault Testing in FPGAs , 2002, Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002).