Implementation of Feed forward and Feedback Neural Network for Signal Processing Using Analog VLSI Technology

Artificial intelligence through a biological world is realized based on mathematical equations and artificial neurons. Main focus is on the implementation of Feedforward and Feedback Neural Network Architecture (NNA) with on a chip learning in analog VLSI for generic signal processing applications. In the proposed project analog components like Gilbert Cell Multiplier (GCM), Neuron Activation Function (NAF) are used to implement artificial Feedforward and Feedback NNA. The analog components used are comprises of multipliers and adders' along with the tan-sigmoid function circuit using MOS transistor in sub threshold region. This neural architecture is trained using Back propagation algorithm in analog domain with new techniques of weight storage. For the proposed design of Feedforward and Feedback Neural Network layout and simulation results are drawn using VLSI Backend Microwind 3.1 software using CMOS 32nm Analog VLSI technology.

[1]  B. Nauta,et al.  Analog circuits in ultra-deep-submicron CMOS , 2005, IEEE Journal of Solid-State Circuits.

[2]  Publisher Ssrg SRG International Journal of Electronics and Communication Engineering (SSRG-IJECE) , 2014 .

[3]  Y. Le Cun,et al.  VLSI implementations of electronic neural networks: an example in character recognition , 1990, 1990 IEEE International Conference on Systems, Man, and Cybernetics Conference Proceedings.

[4]  Yogesh Kumar,et al.  Analog VLSI Implementation of Neural Network Architecture for Signal Processing , 2012, VLSIC 2012.

[5]  Radu Dogaru,et al.  A modified RBF neural network for efficient current-mode VLSI implementation , 1996, Proceedings of Fifth International Conference on Microelectronics for Neural Networks.

[6]  Trond Ytterdal,et al.  Analog Circuit Design in Nanoscale CMOS Technologies , 2009, Proceedings of the IEEE.

[7]  Eric A. Vittoz The Design of High-Performance Analog Circuits on Digital CMOS Chips , 1985 .

[8]  Oscal T.-C. Chen,et al.  A VLSI neural processor for image data compression using self-organization networks , 1992, IEEE Trans. Neural Networks.