A swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications

Swing restored pass-transistor logic (SRPL), a high-speed, low-power logic circuit technique for VLSI applications, is described. By the use of a pass-transistor network to perform logic evaluation and a latch-type swing restoring circuit to drive gate outputs, this technique renders highly competitive circuit performance. An SRPL based multiply and accumulate circuit for multimedia applications is implemented in double metal 0.4 /spl mu/m CMOS technology.

[1]  L. Heller,et al.  Cascode voltage switch logic: A differential CMOS logic family , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  Vojin G. Oklobdzija,et al.  Test Generation for FET Switching Circuits , 1984, ITC.

[3]  Lee-Sup Kim,et al.  200 MHz video compression macrocells using low-swing differential logic , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[4]  Kazuo Yano,et al.  A 3.8 ns CMOS 16×16 multiplier using complementary pass transistor logic , 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

[5]  F. S. Lai,et al.  Differential cascode voltage switch with the pass-gate (DCVSPG) logic tree for high performance CMOS digital systems , 1993, 1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers.

[6]  T. Yamanaka,et al.  A 1.5 ns 32 b CMOS ALU in double pass-transistor logic , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.