Power-balanced reconfigurable floating-gate-MOS logic circuit for tamper resistant VLSI
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[1] Tadashi Shibata,et al. Neuron MOS binary-logic integrated circuits. I. Design fundamentals and soft-hardware-logic circuit implementation , 1993 .
[2] Narayanan Vijaykrishnan,et al. Masking the Energy Behavior of DES Encryption , 2003, DATE.
[3] Luca Benini,et al. Energy-aware design techniques for differential power analysis protection , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[4] Tadashi Shibata,et al. Clock-controlled neuron-MOS logic gates , 1998 .
[5] V.G. Oklobdzija,et al. Improved sense-amplifier-based flip-flop: design and measurements , 2000, IEEE Journal of Solid-State Circuits.
[6] Wei Zhang,et al. Masking the energy behavior of DES encryption [smart cards] , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[7] Tadashi Shibata,et al. A functional MOS transistor featuring gate-level weighted sum and threshold operations , 1992 .
[8] Tadashi Shibata,et al. Real-time reconfigurable logic circuits using neuron MOS transistors , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[9] Paul C. Kocher,et al. Differential Power Analysis , 1999, CRYPTO.