Skewed-Load Transition Test: Part II, Coverage

A skewed-load transition test is a delay test where the second vector of the delay test pair is a one bit shift over the first vector in the pair. This situation occurs when testing the combinational logic residing between scan chains. This paper concentrates on the issue of coverage in skewed-load transition test. A topological lower bound of the transition test coverage is derived. This bound is shown to work well for the entire family if ISCAS combinational circuits. It is also shown that input ordering plays a key role in the attainable transition fault coverage. The paper describes a heuristic for input ordering that will achieve a nearly optimal transition fault coverage.

[1]  M. Ray Mercer,et al.  Delay Testing Quality in Timing-Optimized Designs , 1991, 1991, Proceedings. International Test Conference.

[2]  John A. Waicukauski,et al.  On computing the sizes of detected delay faults , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[4]  Barry K. Rosen,et al.  Comparison of AC Self-Testing Procedures , 1983, ITC.

[5]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[6]  Jacob Savir.  Skewed-Load Transition Test: Part I, Calculus , 1992, Proceedings International Test Conference 1992.

[7]  Eric Lindbloom,et al.  Transition Fault Simulation , 1987, IEEE Design & Test of Computers.

[8]  Thomas W. Williams,et al.  A logic design structure for LSI testability , 1977, DAC '77.

[9]  Jacob Savir,et al.  AT-SPEED TEST IS NOT NECESSARILY AN AC TEST , 1991, 1991, Proceedings. International Test Conference.

[10]  Jacob Savir,et al.  Random Pattern Testability of Delay Faults , 1988, IEEE Trans. Computers.