论文信息 - MOS multiplier/divider cell for analogue VLSI

MOS multiplier/divider cell for analogue VLSI

A novel all-MOS continuous-time multiplier/divider parameterised cell is introduced. It comprises eight MOS transistors and a single operational amplifier. The new cell is highly reconfigurable, versatile, extremely simple to design and its output is conveniently programmed via DC control voltages. Some of the many applications of the new cell in analogue VLSI signal processing include analogue multiplication, signal squaring, division, signal inversion, amplitude modulation and RMS/DC conversion. Moreover, the new cell is easily extendable to achieve analogue vector multiplication, and hence it lends itself naturally to analogue MOS VLSI implementation of feedback/feedforward neural networks.

Mohammed Ismail | N. I. Khachab

[1] Daniel H. Sheingold,et al. Nonlinear circuits handbook : designing with analog function modules and IC's , 1974 .

[2] Mohammed Ismail,et al. An analog MOS implementation of the synaptic weights for feedback neural nets , 1989, IEEE International Symposium on Circuits and Systems,.

[3] Mohammed Ismail. Four-transistor continuous-time MOS transconductor , 1987 .

[4] B. Song. CMOS RF circuits for data communications applications , 1986 .

[5] Z. Czarnul. Modification of Banu - Tsividis continuous-time integrator structure , 1986 .

[6] Mohammed Ismail,et al. A new MOSFET-C universal filter structure for VLSI , 1987, 1987 Symposium on VLSI Circuits.

[7] Mohammed Ismail,et al. Analog VLSI Implementation of Neural Systems , 2011, The Kluwer International Series in Engineering and Computer Science.

[8] J.N. Babanezhad,et al. A 20-V four-quadrant CMOS analog multiplier , 1985, IEEE Journal of Solid-State Circuits.