论文信息 - On the multiple fault diagnosis of multistage interconnection networks: the lower bound and the CMOS fault model

On the multiple fault diagnosis of multistage interconnection networks: the lower bound and the CMOS fault model

This paper presents new results for diagnosing (detection and location) multistage interconnection networks (MINs) in the presence of multiple faults. Initially, it is proved that the lower bound in the number of tests for multiple fault diagnosis (independent of the assumed fault model for the MIN) is 2/spl times/log/sub 2/N, where N is the number of inputs/outputs of the network. A new fault model is introduced; this fault model is applicable to interconnection networks implemented using CMOS technology. The characterization for diagnosing stuck-open faults is presented.

[1] Glenford J. Myers,et al. The 80960 Microprocessor Architecture , 1988 .

[2] Tse-Yun Feng,et al. Fault-Diagnosis for a Class of Multistage Interconnection Networks , 1981, IEEE Trans. Computers.

[3] William J. Dally,et al. A VLSI Architecture for Concurrent Data Structures , 1987 .

[4] Fabrizio Lombardi,et al. Detection and Location of Multiple Faults in Baseline Interconnection Networks , 1992, IEEE Trans. Computers.

[5] Sudhakar M. Reddy,et al. Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits , 1986, IEEE Transactions on Computers.

[6] Fabrizio Lombardi,et al. On the Constant Diagnosability of Baseline Interconnection Networks , 1990, IEEE Trans. Computers.

[7] R. L. Wadsack,et al. Fault modeling and logic simulation of CMOS and MOS integrated circuits , 1978, The Bell System Technical Journal.

[8] Fabrizio Lombardi,et al. Multiple fault detection and location in WSI baseline interconnection networks , 1990, 1990 Proceedings. International Conference on Wafer Scale Integration.

[9] Dharma P. Agrawal,et al. Proceedings of the 11th annual international symposium on Computer architecture , 1984 .

[10] Edward J. McCluskey,et al. Logic design principles - with emphasis on testable semicustom circuits , 1986, Prentice Hall series in computer engineering.