Impact of PVT variability on 20 nm FinFET standard cells

Abstract FinFET technology is pointed as the main candidate to replace CMOS bulk process in sub-22 nm circuits. Predictive technology and design exploration help to understand significant effects of variability sources and their impact on circuit performance and power consumption. This paper evaluates the impact of process, voltage and temperature (PVT) variations on timing and total power of predictive standard cells in 20 nm FinFETs technology node. Results emphasize that standard cell designs in future technologies have to take into account PVT variability in the early steps of the design.

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