On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs

Through Silicon Vias (TSVs) are known to be susceptible to various thermal-mechanical and electro-migration effects that could lead to unexpected resistance increase after certain time of field operation. To cope with this reliability threat, we present an on-line monitoring method that aims to continuously detect excessive transition time occurring to a TSV (which often indicates performance degradation). Our method attaches a monitor to the termination end of a TSV. Any transition there is converted into a pulse-width, which is further compared to a dynamically tunable threshold. A Timing Failure Threat (TFT) is thereby detected when the pulse-width exceeds the threshold. This method can be applied to a large number of TSVs easily since the monitoring results are binary and can be stored in FFs forming a scan chain for easy access.

[1]  Chun-Lung Hsu,et al.  Built-in self-test/repair scheme for TSV-based three-dimensional integrated circuits , 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

[2]  L. Arnaud,et al.  Electromigration behavior of 3D-IC TSV interconnects , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[3]  Ding-Ming Kwai,et al.  A built-in self-test scheme for the post-bond test of TSVs in 3D ICs , 2011, 29th VLSI Test Symposium.

[4]  S. L. Wright,et al.  Micro-interconnection reliability: Thermal, electrical and mechanical stress , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[5]  Yu-Jen Huang,et al.  Built-In Self-Repair Scheme for the TSVs in 3-D ICs , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Qiang Xu,et al.  On effective and efficient in-field TSV repair for stacked 3D ICs , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[7]  Fangming Ye,et al.  TSV open defects in 3D integrated circuits: Characterization, test, and optimal spare allocation , 2012, DAC Design Automation Conference 2012.

[8]  Young-Hyun Jun,et al.  8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology , 2009, IEEE Journal of Solid-State Circuits.

[9]  Jaume Abella,et al.  Microarchitectural Online Testing for Failure Detection in Memory Order Buffers , 2010, IEEE Transactions on Computers.

[10]  Subhasish Mitra,et al.  Overcoming Early-Life Failure and Aging for Robust Systems , 2009, IEEE Design & Test of Computers.

[11]  P. Andry,et al.  Characterization of micro-bump C4 interconnects for Si-carrier SOP applications , 2006, 56th Electronic Components and Technology Conference 2006.

[12]  Qiang Xu,et al.  On effective TSV repair for 3D-stacked ICs , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[13]  L. Arnaud,et al.  Resistance increase due to electromigration induced depletion under TSV , 2011, 2011 International Reliability Physics Symposium.

[14]  C.H. Kim,et al.  Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits , 2007, 2007 IEEE Symposium on VLSI Circuits.

[15]  Suk-kyu Ryu,et al.  Thermal stress induced delamination of through silicon vias in 3-D interconnects , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[16]  Shi-Yu Huang,et al.  Small delay testing for TSVs in 3-D ICs , 2012, DAC Design Automation Conference 2012.

[17]  TingTing Hwang,et al.  TSV redundancy: Architecture and design issues in 3D IC , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[18]  Ankur Srivastava,et al.  Online TSV health monitoring and built-in self-repair to overcome aging , 2013, 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

[19]  Vladimir Pasca,et al.  Through-silicon-via built-in self-repair for aggressive 3D integration , 2012, 2012 IEEE 18th International On-Line Testing Symposium (IOLTS).

[20]  Fangming Ye,et al.  TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).