High Performance THANVaS Memories for MLC Charge Trap NAND Flash

NA

[1]  T. Schram,et al.  Understanding the impact of metal gate on TANOS performance and retention , 2010, 2010 IEEE International Memory Workshop.

[2]  O. Richard,et al.  O2 post deposition anneal of Al2O3 blocking dielectric for higher performance and reliability of TANOS Flash memory , 2009, 2009 Proceedings of the European Solid State Device Research Conference.

[3]  M. Jurczak,et al.  Investigation of Window Instability in Program/Erase Cycling of TANOS NAND Flash Memory , 2009, 2009 IEEE International Memory Workshop.

[4]  Chih-Yuan Lu,et al.  A study of barrier engineered Al2O3 and HfO2 high-K charge trapping devices (BE-MAONOS and BE-MHONOS) with optimal high-K thickness , 2010, 2010 IEEE International Memory Workshop.

[5]  L. Larcher,et al.  Experimental Assessment of Electrons and Holes in Erase Transient of TANOS and TANVaS Memories , 2010, IEEE Electron Device Letters.

[6]  U. Russo,et al.  Experimental and simulation study of the program efficiency of HfO2 based charge trapping memories , 2010, 2010 Proceedings of the European Solid State Device Research Conference.

[7]  M. Rosmeulen,et al.  VARIOT: a novel multilayer tunnel barrier concept for low-voltage nonvolatile memory devices , 2003, IEEE Electron Device Letters.

[8]  R. Degraeve,et al.  Resolving fast VTH transients after program/erase of flash memory stacks and their relation to electron and hole defects , 2009, International Electron Devices Meeting.

[9]  R. Degraeve,et al.  Explanation of anomalous erase behaviour and the associated device instability in TANOS Flash using a new trap characterization technique , 2009 .

[10]  R. Degraeve,et al.  Nitride Engineering for Improved Erase Performance and Retention of TANOS NAND Flash Memory , 2008, 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design.