Trigger voltage walk-in effect of ESD protection device in HVCMOS

Transmission Line Pulse (TLP) curve of high voltage SCR-LDMOS (SCR embedded in LDMOS) is measured under various repetitious TLP stress to evaluate its Electrostatic Discharge (ESD) protection capability. Results show that trigger voltage has walk-in behavior. TCAD simulation indicates its mechanism involved is explained by a base push-out effect dominated melt filament growth, that turns a robust ESD clamp into a fragile device susceptible to trigger voltage collapse.

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