Peak power constrained test sets: generation heuristics and experiments

Life-cycle and reliability of an electronic device are strictly related to the maximum (or peak) power the device dissipates in a single clock cycle. Particular care in situations of peak power violations should be taken in the testing phase of the design process. In such phase, the correctness of the circuit is checked by applying at its primary inputs a set of patterns properly selected with the purpose of detecting the presence of some faults. In a previous work we have addressed the problem of minimizing the peak power of a given combinational test set. The solution we have proposed generates test sets that guarantee a reduced peak power consumption at no penalty in fault coverage. In this paper, we present heuristic variants to the algorithm mentioned above. Such variants aim at increasing the efficiency of the test set, that is, they help better in controlling the size of the modified test set. We also investigate the impact of some of the parameters of the algorithm on the quality of the modified test set, and we support the conclusions we have drawn from the discussion with a large set of experimental data that we have collected on the Iscas'85 combinational benchmark circuits.