Multiprocessor System-on-Chip (MPSoC) Technology

The multiprocessor system-on-chip (MPSoC) uses multiple CPUs along with other hardware subsystems to implement a system. A wide range of MPSoC architectures have been developed over the past decade. This paper surveys the history of MPSoCs to argue that they represent an important and distinct category of computer architecture. We consider some of the technological trends that have driven the design of MPSoCs. We also survey computer-aided design problems relevant to the design of MPSoCs.

[1]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[2]  Ahmed Sameh,et al.  The Illiac IV system , 1972 .

[3]  Samuel P. Harbison,et al.  Reflections in a pool of processors - An experience report on C.mmp/Hydra , 1978, AFIPS National Computer Conference.

[4]  Peter Marwedel,et al.  The MIMOLA Design System: Tools for the Design of Digital Processors , 1984, 21st Design Automation Conference Proceedings.

[5]  Allan Gottlieb,et al.  Highly parallel computing , 1989, Benjamin/Cummings Series in computer science and engineering.

[6]  Alvin M. Despain,et al.  Viewing instruction set design as an optimization problem , 1991, MICRO 24.

[7]  Andrew Wolfe,et al.  Executing compressed programs on an embedded RISC architecture , 1992, MICRO.

[8]  Giovanni De Micheli,et al.  Hardware-software cosynthesis for digital systems , 1993, IEEE Design & Test of Computers.

[9]  Jörg Henkel,et al.  Hardware-software cosynthesis for microcontrollers , 1993, IEEE Design & Test of Computers.

[10]  Frank Vahid,et al.  A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning , 1994, EURO-DAC '94.

[11]  Hugo De Man,et al.  Control flow optimization for fast system simulation and storage minimization [real-time multidimens , 1994 .

[12]  Dirk Herrmann,et al.  An approach to the adaptation of estimated cost parameters in the COSYMA system , 1994, Third International Workshop on Hardware/Software Codesign.

[13]  Allan Gottlieb,et al.  Highly parallel computing (2nd ed.) , 1994 .

[14]  An approach to the adaptation of estimated cost parameters in the COSYMA system , 1994, CODES '94.

[15]  Mircea R. Stan,et al.  Bus-invert coding for low-power I/O , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[16]  Hugo De Man,et al.  Memory organization for video algorithms on programmable signal processors , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[17]  Ing-Jer Huang,et al.  Synthesis of application specific instruction sets , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Frank Vahid,et al.  Incremental hardware estimation during hardware/software functional partitioning , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[19]  Hugo De Man,et al.  CoWare—A design environment for heterogeneous hardware/software systems , 1996, EURO-DAC '96/EURO-VHDL '96.

[20]  Arun N. Netravali,et al.  Digital Video: An introduction to MPEG-2 , 1996 .

[21]  Edward A. Lee,et al.  The Extended Partitioning Problem: Hardware/Software Mapping, Scheduling, and Implementation-bin Selection , 1997, Des. Autom. Embed. Syst..

[22]  Anne Elisabeth Haxthausen,et al.  LYCOS: the Lyngby Co-Synthesis System , 1997, Des. Autom. Embed. Syst..

[23]  Jung-Hsien Chiang,et al.  Neural and Fuzzy Methods in Handwriting Recognition , 1997, Computer.

[24]  Trevor N. Mudge,et al.  Improving code density using compression techniques , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[25]  Marilyn Wolf,et al.  An architectural co-synthesis algorithm for distributed, embedded computing systems , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[26]  Nikil D. Dutt,et al.  Memory data organization for improved cache performance in embedded processor applications , 1997, TODE.

[27]  Kunle Olukotun,et al.  A Single-Chip Multiprocessor , 1997, Computer.

[28]  Petru Eles,et al.  System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search , 1997, Des. Autom. Embed. Syst..

[29]  Luca Benini,et al.  Power optimization of core-based systems by address bus encoding , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[30]  Robert K. Montoye,et al.  A decompression core for PowerPC , 1998, IBM J. Res. Dev..

[31]  Anoop Gupta,et al.  Parallel computer architecture - a hardware / software approach , 1998 .

[32]  Niraj K. Jha,et al.  MOGAC: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[33]  Tomás Lang,et al.  Working-zone encoding for reducing the energy in microprocessor address buses , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[34]  E. Sackinger,et al.  A single-chip, 1.6-billion, 16-b MAC/s multiprocessor DSP , 2000, IEEE Journal of Solid-State Circuits.

[35]  Niraj K. Jha,et al.  COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[36]  Thomas M. Conte,et al.  Compiler-driven cached code compression schemes for embedded ILP processors , 1999, MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture.

[37]  F. Schirrmeister,et al.  Methodology and technology for virtual component driven hardware/software co-design on the system-level , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[38]  F. Catthoor,et al.  A performance-oriented use methodology of power optimizing code transformations for multimedia applications realized on programmable multimedia processors , 1999, 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461).

[39]  Wayne H. Wolf,et al.  SAMC: a code compression algorithm for embedded processors , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[40]  Mahmut T. Kandemir,et al.  Improving Cache Locality by a Combination of Loop and Data Transformation , 1999, IEEE Trans. Computers.

[41]  B. Ramakrishna Rau,et al.  Automatic architectural synthesis of VLIW and EPIC processors , 1999, Proceedings 12th International Symposium on System Synthesis.

[42]  Giovanni De Micheli,et al.  Hardware/Software Co-Design of Run-Time Schedulers for Real-Time Systems , 2000, Des. Autom. Embed. Syst..

[43]  Nikil D. Dutt,et al.  On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems , 2000, TODE.

[44]  Drew Wingard.  MicroNetwork-based integration for SOCs , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[45]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[46]  Jean-Marc Daveau,et al.  Automating the Design of SOCs Using Cores , 2001, IEEE Des. Test Comput..

[47]  Heinrich Meyr,et al.  A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[48]  Santanu Dutta,et al.  Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems , 2001, IEEE Des. Test Comput..

[49]  Michael E. Wazlowski,et al.  IBM Memory Expansion Technology (MXT) , 2001, IBM J. Res. Dev..

[50]  Jörg Henkel,et al.  An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[51]  Wayne Wolf,et al.  Modern vlsi design: system-on-chip design, third edition , 2002 .

[52]  Luca Benini,et al.  Hardware-assisted data compression for energy minimization in systems with embedded processors , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[53]  Paolo Ienne,et al.  Automatic application-specific instruction-set extensions under microarchitectural constraints , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[54]  Jörg Henkel,et al.  A dictionary-based en/decoding scheme for low-power data buses , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[55]  Rajeev Balasubramonian,et al.  A Dynamically Tunable Memory Hierarchy , 2003, IEEE Trans. Computers.

[56]  Mahmut T. Kandemir,et al.  Memory system optimization of embedded software , 2003, Proc. IEEE.

[57]  Yoshinori Takeuchi,et al.  Rapid prototyping of JPEG encoder using the ASIP development system: PEAS-III , 2003, 2003 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03)..

[58]  Darin Petkov,et al.  Automatic generation of application specific processors , 2003, CASES '03.

[59]  C. John Glossner,et al.  A software-defined communications baseband design , 2003, IEEE Commun. Mag..

[60]  David Blaauw,et al.  Mobile supercomputers , 2004, Computer.

[61]  Wayne H. Wolf,et al.  The future of multiprocessor systems-on-chips , 2004, Proceedings. 41st Design Automation Conference, 2004..

[62]  Steve Leibson,et al.  Engineering the complex SOC : fast, flexible design with configurable processors , 2004 .

[63]  Nikil D. Dutt,et al.  Automatic tuning of two-level caches to embedded applications , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[64]  John Goodacre,et al.  Parallelism and the ARM instruction set architecture , 2005, Computer.

[65]  Ahmed Amine Jerraya,et al.  Component-Based Design for Multiprocessor Systems-on-Chips , 2005 .

[66]  Simcha Gochman,et al.  Introduction to Intel Core Duo Processor Architecture , 2006 .

[67]  Jörg Henkel,et al.  A design methodology for application-specific networks-on-chip , 2006, TECS.

[68]  Fabrizio Petrini,et al.  Cell Multiprocessor Communication Network: Built for Speed , 2006, IEEE Micro.

[69]  Luca Benini,et al.  Networks on chips - technology and tools , 2006, The Morgan Kaufmann series in systems on silicon.

[70]  Brian Bailey,et al.  ESL Design and Verification: A Prescription for Electronic System Level Methodology , 2007 .

[71]  Ahmed Amine Jerraya,et al.  Efficient Software Development Platforms for Multimedia Applications at Different Abstraction Levels , 2007, 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07).

[72]  David A. Patterson,et al.  Computer Architecture - A Quantitative Approach (4. ed.) , 2007 .

[73]  Jinuk Luke Shin,et al.  A Power-Efficient High-Throughput 32-Thread SPARC Processor , 2007, IEEE Journal of Solid-State Circuits.

[74]  Rolf Drechsler,et al.  ESL Design and Verification , 2010 .