Design error diagnosis based on verification techniques [logic IC design]

Error diagnosis is becoming more difficult in VLSI circuit designs due to the increasing complexity. In this paper, we present an algorithm based on verification for improving the accuracy of design error diagnosis. This algorithm integrates three-valued logic simulation and Boolean satisfiability (SAT). It uses test patterns generated by a gate level stuck-at fault ATPG tool for parallel pattern simulation, and uses SAT-based Boolean comparison to enhance the three-valued simulation, in which universally quantified conjunction normal formulas (CNF) represent the unknown constraints in the implementation with black boxes, and does not need circuit structural transformation. Our approach can quickly and efficiently eliminate many false candidates, experimental results on ISCAS'85 circuits show the accuracy and the speed of this approach.

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