A 4 channel analog front end for central office ADSL modems

This chip integrates a 4 channel analog front-end for central office ADSL modems. The receive path has a programmable gain amplifier (PGA) with 30 dB of range followed by a fourth-order 2-bit sigma-delta modulator clocking at 35 MHz. The transmit path uses a 14-bit current steering D/A converter followed by a fourth-order low-pass filter. The device is implemented in 0.35 /spl mu/m CMOS and consumes less than 160 mW per channel. It is packaged in a 100 pin MQFP package.

[1]  Xiaomin Si,et al.  A CMOS analog front-end IC for DMT ADSL , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[2]  L. R. Carley,et al.  A 16-bit 4'th order noise-shaping D/A converter , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[3]  Stephen H. Lewis,et al.  A second-order double-sampled delta-sigma modulator using additive-error switching , 1996 .

[4]  Lawrence A. Singer,et al.  12-b 125 MSPS CMOS D/A designed for spectral performance , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

[5]  R. Adams,et al.  A stereo multi-bit /spl Sigma//spl Delta/ D/A with asynchronous master-clock interface , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.