FBM: A Simple and Fast Algorithm for Placement Legalization

In VLSI physical design, the legalization step has to deal with thousands of logic cells that need to provide a placement solution with all cells aligned within the rows and overlap-free, while preserving the global placement solution, i.e., displacement should minimize. We present an algorithm for VLSI placement legalization that minimizes the impact of wirelength in high-density circuits. Our approach is based first on sorting the cells according to their positions and legalizing each pair of overlapping cells. The algorithm moves the second overlap cell to the right until it finds a legalized placement with the lowest movement. Our experimental results show that our algorithm can reduce the runtime with a minimum impact on wirelength when compared to another legalization tool.