A fast MPSoC virtual prototyping for intensive signal processing applications

Due to the growing computation rates of intensive signal processing applications, using Multiprocessor System on Chip (MPSoC) becomes an incontrovertible solution to meet the functional requirements. Today, Electronic System Level (ESL) design is considered a vital premise to overcome the design complexity intrinsic in the heterogeneity of these devices. However, the development of tools at the system level is in the face of extremely challenging requirements such as the rapid system prototyping, the accurate performance estimation, and the reliable design space exploration (DSE). Focusing on the issue of ESL development tools, this paper describes an MPSoC environment design which targets the Multidimensional Intensive Signal Processing (MISP) application domain. Within this environment, we have defined first a generic execution model that supports any type of MPSoC. It can adapt to any parallel application and handle efficiently the scheduling and synchronizations at all the levels of granularity. Second, a new Virtual Processor (VP) based simulation technique is proposed for implementing the execution model. This proposal leverages the high-level specification of the system to provide a heterogeneous MPSoCs simulation without using an Instruction Set Simulator (ISS). VP-based simulation is implemented in SystemC at a timed transactional level allowing a good trade-off between high simulation speed and performance estimation accuracy. The usefulness and the effectiveness of our MPSoC environment is illustrated through two MISP applications executed on a typical MPSoC. Results show that our approach enables fast MPSoC virtual prototyping, data transfers and timing analysis, and reliable DSE for architectural optimizations.

[1]  Thomas F. Wenisch,et al.  SMARTS: accelerating microarchitecture simulation via rigorous statistical sampling , 2003, ISCA '03.

[2]  Douglas C. Schmidt,et al.  Guest Editor's Introduction: Model-Driven Engineering , 2006, Computer.

[3]  Brad Calder,et al.  Discovering and Exploiting Program Phases , 2003, IEEE Micro.

[4]  Pierre Boulet,et al.  Distributed Process Networks - Using Half FIFO Queues in CORBA , 2003, PARCO.

[5]  Jean-Luc Dekeyser,et al.  Model Driven Engineering Benefits for High Level Synthesis , 2008 .

[6]  Thomas Martyn Parks,et al.  Bounded scheduling of process networks , 1996 .

[7]  E.A. Lee,et al.  Synchronous data flow , 1987, Proceedings of the IEEE.

[8]  Jean-Luc Dekeyser,et al.  An MPSoC Performance Estimation Framework Using Transaction Level Modeling , 2007, 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007).

[9]  Luca Fossati,et al.  ReSP: A Nonintrusive Transaction-Level Reflective MPSoC Simulation Platform for Design Space Exploration , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Ahmed Amine Jerraya,et al.  Multiprocessor System-on-Chip (MPSoC) Technology , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Luca Benini,et al.  SystemC Cosimulation and Emulation of Multiprocessor SoC Designs , 2003, Computer.

[12]  Philippe Dumont Spécification multidimensionnelle pour le traitement du signal systématique , 2005 .

[13]  Brian Bailey System Level Virtual Prototyping becomes a reality with OVP donation from Imperas. , 2008 .

[14]  J. Lee,et al.  Hardware-software co-implementation of a H.263 video codec , 2000, IEEE Trans. Consumer Electron..

[15]  Daniel Gajski,et al.  Transaction level modeling: an overview , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

[16]  Edward A. Lee,et al.  Scheduling dynamic dataflow graphs with bounded memory using the token flow model , 1993, 1993 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[17]  Jean-Luc Dekeyser,et al.  Model Transformations for the Compilation of Multi-processor Systems-on-Chip , 2007, GTTSE.

[18]  Pierre Boulet,et al.  Formal Semantics of Array-OL, a Domain Specific Language for Intensive Multidimensional Signal Processing , 2008 .

[19]  Hiroaki Takada,et al.  RTOS-centric hardware/software cosimulator for embedded system design , 2004, International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004..

[20]  Edward A. Lee,et al.  Design and implementation of a multidimensional synchronous dataflow environment , 1994, Proceedings of 1994 28th Asilomar Conference on Signals, Systems and Computers.

[21]  Pierre Boulet,et al.  Repetitive Allocation Modelling with MARTE , 2007, FDL.

[22]  Pierre Boulet,et al.  Gaspard2: from MARTE to SystemC Simulation , 2008 .

[23]  Multiprocessor performance estimation using hybrid simulation , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[24]  Gilles Kahn,et al.  The Semantics of a Simple Language for Parallel Programming , 1974, IFIP Congress.

[25]  Stuart Kent,et al.  Model Driven Engineering , 2002, IFM.