A fundamental limit of CMOS supply-voltage (V/sub CC/) scaling has been investigated and quantified as a function of the statistical variation of MOSFET threshold-voltage (V/sub T/). Based on the data extracted from a sub-0.5 /spl mu/m logic technology, the variation of ring-oscillator propagation-delay (T/sub PD/) significantly increases as V/sub CC/ is scaled down towards the MOSFET V/sub T/ (Fig. 1). An empirical power-law relationship was then derived to describe the scattering of circuit speed (/spl Delta/T/sub PD/) as a function of MOSFET V/sub T/ variation(/spl Delta/V/sub T/) and (V/sub CC/-V/sub T/). Agreement between the model and the experimental data was established for V/sub CC/ values from 4.0 V to 0.9 V. This fundamental limit of CMOS V/sub CC/ scaling poses an additional challenge for the design and manufacturing of high-performance, low-power portable equipment and battery based systems.<<ETX>>
[1]
M. Kinugawa,et al.
Power-supply voltage impact on circuit performance for half and lower submicrometer CMOS LSI
,
1990
.
[2]
A. R. Newton,et al.
Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
,
1990
.
[3]
Katsuhiro Shimohigashi,et al.
Low voltage ULSI design: the lower, the better?
,
1992,
1992 Symposium on VLSI Circuits Digest of Technical Papers.
[4]
Paul G. Y. Tsui,et al.
A fully complementary BiCMOS technology for sub-half-micrometer microprocessor applications
,
1992
.
[5]
Christer Svensson,et al.
Trading speed for low power by choice of supply and threshold voltages
,
1993
.