A 32mW 7.4Gb/s protocol-agile source-series-terminated transmitter in 45nm CMOS SOI

Source-series-terminated (SST) transmitters consume ¼ the output stage power of CML drivers [1], but their adoption in industry-standard multi-protocol SerDes has been stunted by difficulties in achieving flexible swings, constant current equalization, and supporting DC-coupled voltage standards drafted with CML in mind. Fundamentally, CML drivers separate the termination control from the switching devices, allowing current summing techniques to implement output level control and transmitter equalization (EQ). In this paper, the architecture and circuits of an equally flexible SST transmitter is presented that overcomes these challenges through the use of ground regulation, P-to-N shunting legs, and partially weighted segments. The clocks and datapath dissipate 32mW at 7.4Gb/s with an 800mV differential swing. Target protocols include PCIe Gen, XAUI, Fibre Channel (FC) 1/2/4, CEI6 SR and SATA .

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