Multi-ASIP platform synthesis for real-time applications

In this paper we are interested in deriving a distributed platform, composed of heterogeneous processing elements, targeted to applications that have strict timing constraints. We consider that the platform may use multiple Application Specific Instruction Set Processors (ASIPs). An ASIP is synthesized and tuned for a specific set of tasks (i.e., a task cluster). During design space exploration (DSE), we evaluate each platform solution visited in terms of its cost and performance, i.e., its ability to execute the applications such that they meet their timing constraints. To determine if the applications are schedulable, we have to know the worst-case execution time (WCET) of each task. However, we can determine the WCETs only after the ASIPs are synthesized, which is time consuming and therefore cannot be done during DSE. To address this circular dependency (the ASIPs depend on the task clustering, and the WCETs of tasks, used to determine schedulability, depend on how ASIPs are synthesized), we propose an uncertainty model for the WCETs, which captures the range of possible ASIP implementations. Based on this model, we synthesize a multi-ASIP platform, such that the applications have a high chance of being schedulable and the cost constraints imposed on the platform are fulfilled. We propose an Evolutionary Algorithm-based approach, which uses a novel stochastic schedulability analysis to solve this optimization problem. The proposed approach has been evaluated using several benchmarks.

[1]  Graham Kendall,et al.  Search Methodologies: Introductory Tutorials in Optimization and Decision Support Techniques , 2013 .

[2]  Achim Nohl,et al.  Application specific processor design: Architectures, design methods and tools , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[3]  Timo Hämäläinen,et al.  UML-based multiprocessor SoC design framework , 2006, TECS.

[4]  Amer Baghdadi,et al.  From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Lech Józwiak,et al.  Issues and Challenges in Development of Massively-Parallel Heterogeneous MPSoCs Based on Adaptable ASIPs , 2011, 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing.

[6]  Luca Fanucci,et al.  Algorithmic and architectural design for real-time and power-efficient Retinex image/video processing , 2007, Journal of Real-Time Image Processing.

[7]  Sri Parameswaran,et al.  Multi-ASIP based parallel and scalable implementation of motion estimation kernel for high definition videos , 2011, 2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia.

[8]  Yan Alexander Li,et al.  Estimating the execution time distribution for a task graph in a heterogeneous computing system , 1997, Proceedings Sixth Heterogeneous Computing Workshop (HCW'97).

[9]  Y.-K. Kwok,et al.  Static scheduling algorithms for allocating directed task graphs to multiprocessors , 1999, CSUR.

[10]  Yajun Ha,et al.  Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA , 2008, TODE.

[11]  Jakob Axelsson,et al.  A method for evaluating uncertainties in the early development phases of embedded real-time systems , 2005, 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'05).

[12]  Kingshuk Karuri,et al.  A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs) , 2009, SAMOS.

[13]  Petru Eles,et al.  Holistic scheduling and analysis of mixed time/event-triggered distributed embedded systems , 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).

[14]  Robert A. Walker,et al.  Introduction to the Scheduling Problem , 1995, IEEE Des. Test Comput..

[15]  Anshul Kumar,et al.  ASIP design methodologies: survey and issues , 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

[16]  Dimitrios Kritharidis,et al.  Application of the MOSART Flow on the WiMAX (802.16e) PHY Layer , 2012 .

[17]  Sri Parameswaran,et al.  Design Methodology for Pipelined Heterogeneous Multiprocessor System , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[18]  Norbert Wehn,et al.  A scalable multi-ASIP architecture for standard compliant trellis decoding , 2011, 2011 International SoC Design Conference.

[19]  Henk Corporaal,et al.  An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems on Chip , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[20]  Ed F. Deprettere,et al.  Systematic and Automated Multiprocessor System Design, Programming, and Implementation , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  Ludovic Apvrille,et al.  Evaluation of ASIPs Design with LISATek , 2008, SAMOS.

[22]  Sri Parameswaran,et al.  Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study , 2008, CODES+ISSS '08.