TITAC-2: an asynchronous 32-bit microprocessor

With the wire-delay problem moving into dominance in VLSI chip design, a fundamental limitation is being revealed in performance and dependability of synchronous systems which require global clock distribution with as little skew as possible. The worst-case delay is influenced not only by design and fabrication process but also by the operating environment, e.g. the power supply voltage and temperature. Asynchronous systems, with no global clock, can intrinsically enjoy: 1) average case performance instead of worst-case performance, 2) low power consumption, 3) ease of modular design, and 4) timing fault tolerance. We have designed and implemented a 32-bit fully asynchronous microprocessor, TITAC-2, which is the fastest and largest CMOS asynchronous microprocessor that has ever been operational.

[1]  Takashi Nanya,et al.  TITAC-2: an asynchronous 32-bit microprocessor based on scalable-delay-insensitive model , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[2]  T. Nanya TITAC-2 : A 32-bit scalable-delay-insensitive microprocessor , 1997 .